{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T10:51:22Z","timestamp":1730199082609,"version":"3.28.0"},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,11,7]],"date-time":"2021-11-07T00:00:00Z","timestamp":1636243200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,11,7]],"date-time":"2021-11-07T00:00:00Z","timestamp":1636243200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,11,7]],"date-time":"2021-11-07T00:00:00Z","timestamp":1636243200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,11,7]]},"DOI":"10.1109\/a-sscc53895.2021.9634179","type":"proceedings-article","created":{"date-parts":[[2021,12,10]],"date-time":"2021-12-10T20:45:05Z","timestamp":1639169105000},"page":"1-3","source":"Crossref","is-referenced-by-count":3,"title":["A 21Gb\/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer"],"prefix":"10.1109","author":[{"given":"Jae-Woo","family":"Park","sequence":"first","affiliation":[]},{"given":"Dongsuk","family":"Kang","sequence":"additional","affiliation":[]},{"given":"Injae","family":"Park","sequence":"additional","affiliation":[]},{"given":"Minsu","family":"Park","sequence":"additional","affiliation":[]},{"given":"Xuefan","family":"Jin","sequence":"additional","affiliation":[]},{"given":"Kyu-Dong","family":"Hwang","sequence":"additional","affiliation":[]},{"given":"Dae-Han","family":"Kwon","sequence":"additional","affiliation":[]},{"given":"Jung-Hoon","family":"Chun","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2675923"},{"key":"ref3","article-title":"An 18 Gb\/s duobinary receiver with a CDRassisted DFE","author":"sunaga","year":"2009","journal-title":"IEEE ISSCC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1493873"},{"key":"ref2","first-page":"197","article-title":"A 16-Gb, 18Gb\/s\/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking","volume":"50","author":"kim","year":"2019","journal-title":"JSSC"},{"journal-title":"JESD 205B","article-title":"GRAPHICS DUOBLE DATA RATE 6 (GDDR6) SGRAM STANDARD","year":"2018","key":"ref1"}],"event":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","start":{"date-parts":[[2021,11,7]]},"location":"Busan, Korea, Republic of","end":{"date-parts":[[2021,11,10]]}},"container-title":["2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9634699\/9634177\/09634179.pdf?arnumber=9634179","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:54:28Z","timestamp":1652201668000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9634179\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11,7]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/a-sscc53895.2021.9634179","relation":{},"subject":[],"published":{"date-parts":[[2021,11,7]]}}}