{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T16:20:56Z","timestamp":1694622056066},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2001,7,1]],"date-time":"2001-07-01T00:00:00Z","timestamp":993945600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2001,7]]},"DOI":"10.1109\/4.933470","type":"journal-article","created":{"date-parts":[[2002,8,24]],"date-time":"2002-08-24T18:32:16Z","timestamp":1030213936000},"page":"1120-1126","source":"Crossref","is-referenced-by-count":4,"title":["A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs"],"prefix":"10.1109","volume":"36","author":[{"given":"H.","family":"Fujisawa","sequence":"first","affiliation":[]},{"given":"T.","family":"Takahashi","sequence":"additional","affiliation":[]},{"given":"M.","family":"Nakamura","sequence":"additional","affiliation":[]},{"given":"K.","family":"Kujigaya","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.799867"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.475703"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.98963"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1992.229240"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/4.726566"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.245586"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.535412"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.823441"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.799866"},{"key":"ref9","first-page":"376","article-title":"a dual-phase-controlled dynamic latched (ddl) amplifier for high-speed and low-power drams","author":"fujisawa","year":"2000","journal-title":"Proc 26th Eur Solid-State Circuits Conf"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/20201\/00933470.pdf?arnumber=933470","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:07:36Z","timestamp":1638216456000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/933470\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001,7]]},"references-count":10,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/4.933470","relation":{},"ISSN":["0018-9200"],"issn-type":[{"value":"0018-9200","type":"print"}],"subject":[],"published":{"date-parts":[[2001,7]]}}}