{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T17:26:12Z","timestamp":1694625972278},"reference-count":8,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2001,4,1]],"date-time":"2001-04-01T00:00:00Z","timestamp":986083200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2001,4]]},"DOI":"10.1109\/4.913743","type":"journal-article","created":{"date-parts":[[2002,8,24]],"date-time":"2002-08-24T18:17:23Z","timestamp":1030213043000},"page":"648-657","source":"Crossref","is-referenced-by-count":6,"title":["A 500-Mb\/s quadruple data rate SDRAM interface using a skew cancellation technique"],"prefix":"10.1109","volume":"36","author":[{"family":"Sung-Ho Wang","sequence":"first","affiliation":[]},{"family":"Jeongpyo Kim","sequence":"additional","affiliation":[]},{"family":"Joonsuk Lee","sequence":"additional","affiliation":[]},{"family":"Hyoung Sik Nam","sequence":"additional","affiliation":[]},{"family":"Young Gon Kim","sequence":"additional","affiliation":[]},{"family":"Jae Hoon Shim","sequence":"additional","affiliation":[]},{"family":"Hyung Ki Ahn","sequence":"additional","affiliation":[]},{"family":"Seok Kang","sequence":"additional","affiliation":[]},{"family":"Bong Hwa Jeong","sequence":"additional","affiliation":[]},{"family":"Jin Hong Ahn","sequence":"additional","affiliation":[]},{"family":"Beomsup Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1999.759333"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1999.759327"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.340422"},{"key":"ref5","first-page":"18","year":"1998","journal-title":"Detailed functionality description for DDR SDRAM"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"1385","DOI":"10.1109\/4.62166","article-title":"a 30-mhz hybrid analog\/digital clock recovery circuit in 2-$\\mu$<\/tex><\/formula>m cmos","volume":"25","author":"kim","year":"1990","journal-title":"IEEE J Solid State Circuits"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1999.759285"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.726569"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1998.672415"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/19725\/00913743.pdf?arnumber=913743","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:07:34Z","timestamp":1638216454000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/913743\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001,4]]},"references-count":8,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/4.913743","relation":{},"ISSN":["0018-9200"],"issn-type":[{"value":"0018-9200","type":"print"}],"subject":[],"published":{"date-parts":[[2001,4]]}}}