乐胖代购免代理版

{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,2]],"date-time":"2023-09-02T19:49:47Z","timestamp":1693684187521},"reference-count":33,"publisher":"Institution of Engineering and Technology (IET)","issue":"1","license":[{"start":{"date-parts":[[2018,9,19]],"date-time":"2018-09-19T00:00:00Z","timestamp":1537315200000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"},{"start":{"date-parts":[[2018,9,19]],"date-time":"2018-09-19T00:00:00Z","timestamp":1537315200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/doi.wiley.com\/10.1002\/tdm_license_1.1"}],"funder":[{"DOI":"10.13039\/501100001843","name":"Science and Engineering Research Board","doi-asserted-by":"publisher","award":["SB\/FTP\/ETA\u201040\/2013"],"id":[{"id":"10.13039\/501100001843","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IET Computers & Digital Techniques"],"published-print":{"date-parts":[[2019,1]]},"DOI":"10.1049\/iet-cdt.2018.5067","type":"journal-article","created":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T02:29:44Z","timestamp":1535768984000},"page":"49-56","source":"Crossref","is-referenced-by-count":1,"title":["Investigating the role of interconnect surface roughness towards the design of power\u2010aware network on chip"],"prefix":"10.1049","volume":"13","author":[{"given":"Somesh","family":"Kumar","sequence":"first","affiliation":[{"name":"Department of Electrical EngineeringIndian Institute of Technology RoparNangal RoadRupnagarIndia"}]},{"ORCID":"http:\/\/orcid.org\/0000-0002-7795-7551","authenticated-orcid":false,"given":"Rohit","family":"Sharma","sequence":"additional","affiliation":[{"name":"Department of Electrical EngineeringIndian Institute of Technology RoparNangal RoadRupnagarIndia"}]}],"member":"265","published-online":{"date-parts":[[2018,9,19]]},"reference":[{"issue":"2","key":"e_1_2_6_2_2","doi-asserted-by":"crossref","first-page":"261","DOI":"10.1049\/ip-cdt:20045100","article-title":"Network\u2010on\u2010chip architectures and design methods","volume":"152","author":"Benini L.","year":"2005","journal-title":"IEE Proc., Comput. Digit. Tech."},{"issue":"1","key":"e_1_2_6_3_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1736065.1736069","article-title":"An analysis of on\u2010chip interconnection networks for large\u2010scale chip multiprocessors","volume":"7","author":"Sanchez D.","year":"2010","journal-title":"ACM Trans. Archit. Code Optim."},{"key":"e_1_2_6_4_2","doi-asserted-by":"crossref","unstructured":"Balfour J. Dally W.J.: \u2018Design tradeoffs for tiled CMP on\u2010chip networks\u2019.Proc. 20th Annual Int. Conf. on Supercomputing 2006","DOI":"10.1145\/1183401.1183430"},{"issue":"5","key":"e_1_2_6_5_2","doi-asserted-by":"crossref","first-page":"430","DOI":"10.1109\/MDT.2008.137","article-title":"Characterization of equalized and repeated interconnects for NoC applications","volume":"25","author":"Kim B.","year":"2008","journal-title":"IEEE Des. Test Comput."},{"key":"e_1_2_6_6_2","unstructured":"International Technology Working Groups: \u2018International technology roadmap for semiconductors\u2019 2013"},{"key":"e_1_2_6_7_2","doi-asserted-by":"crossref","unstructured":"Kumar S. Sharma R.: \u2018Design space exploration of nanoscale interconnects with rough surfaces\u2019.IEEE Electrical Design of Advanced Packaging and Systems Symp. (EDAPS) 2015","DOI":"10.1109\/EDAPS.2015.7383683"},{"issue":"23","key":"e_1_2_6_8_2","doi-asserted-by":"crossref","first-page":"235423","DOI":"10.1103\/PhysRevB.84.235423","article-title":"Electron scattering at surfaces and grain boundaries in Cu thin films and wires","volume":"84","author":"Chawla J.S.","year":"2011","journal-title":"Phys. Rev. B"},{"key":"e_1_2_6_9_2","article-title":"Analytical model for resistivity and mean free path in on\u2010chip interconnects with rough surfaces","author":"Kumar S.","year":"2016","journal-title":"IEEE Trans. Emerg. Top. Comput."},{"issue":"20","key":"e_1_2_6_10_2","doi-asserted-by":"crossref","first-page":"2692","DOI":"10.1088\/0022-3727\/32\/20\/317","article-title":"Rough\u2010surface capacitor: approximations of the capacitance with elementary functions","volume":"32","author":"Bruce N.C.","year":"1999","journal-title":"J. Phys. D, Appl. Phys."},{"key":"e_1_2_6_11_2","article-title":"Analytical modeling and performance benchmarking of on\u2010chip interconnects with rough surfaces","author":"Kumar S.","year":"2017","journal-title":"IEEE Trans. Multi\u2010Scale Comput. Syst."},{"key":"e_1_2_6_12_2","unstructured":"Sarangi S.R. Kalayappan R. Kallurkar P. et al.: \u2018Tejas simulator: validation against hardware\u2019.25th Int. Workshop on Power and Timing Modeling Optimization and Simulation (PATMOS) 2015"},{"issue":"7","key":"e_1_2_6_13_2","doi-asserted-by":"crossref","first-page":"2071","DOI":"10.1109\/TED.2015.2427033","article-title":"System\u2010level variation analysis for interconnection networks at sub\u201010\u2010Nm technology nodes using multiple patterning techniques","volume":"62","author":"Pan C.","year":"2015","journal-title":"IEEE Trans. Electron Devices"},{"issue":"9","key":"e_1_2_6_14_2","doi-asserted-by":"crossref","first-page":"990","DOI":"10.1109\/TVLSI.2007.902209","article-title":"Design and optimization of on\u2010chip interconnects using wave\u2010pipelined multiplexed routing","volume":"15","author":"Joshi A.J.","year":"2007","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"9","key":"e_1_2_6_15_2","doi-asserted-by":"crossref","first-page":"1376","DOI":"10.1109\/TVLSI.2009.2024118","article-title":"Evaluating carbon nanotube global interconnects for chip multiprocessor applications","volume":"18","author":"Pasricha S.","year":"2010","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"5","key":"e_1_2_6_16_2","doi-asserted-by":"crossref","first-page":"539","DOI":"10.1049\/iet-cdt.2008.0065","article-title":"Application modelling and hardware description for network\u2010on\u2010chip benchmarking","volume":"3","author":"Salminen E.","year":"2009","journal-title":"IET Comput. Digit. Tech."},{"issue":"6","key":"e_1_2_6_17_2","doi-asserted-by":"crossref","first-page":"294","DOI":"10.1049\/iet-cdt.2013.0030","article-title":"Hybrid wire\u2010surface wave interconnects for next\u2010generation networks\u2010on\u2010chip","volume":"7","author":"Karkar A.J.","year":"2013","journal-title":"IET Comput. Digit. Tech."},{"key":"e_1_2_6_18_2","doi-asserted-by":"crossref","unstructured":"Chen F. Joshi A. Stojanovi V. et al.: \u2018Scaling and evaluation of carbon nanotube interconnects for VLSI applications\u2019.Proc. Second Int. Conf. on Nano\u2010Networks 2007","DOI":"10.4108\/ICST.NANONET2007.2041"},{"key":"e_1_2_6_19_2","doi-asserted-by":"crossref","unstructured":"Zarkesh\u2010Ha P. Bezerra G.B.P. Forrest S. et al.: \u2018Hybrid network on chip (HNoC): local buses with a global mesh architecture\u2019.Proc. 12th ACM\/IEEE Int. Workshop on System Level Interconnect Prediction 2010","DOI":"10.1145\/1811100.1811104"},{"issue":"1","key":"e_1_2_6_20_2","doi-asserted-by":"crossref","first-page":"39","DOI":"10.1016\/j.sysarc.2010.07.002","article-title":"Modeling and evaluation of ring\u2010based interconnects for network\u2010on\u2010chip","volume":"57","author":"Bourduas S.","year":"2011","journal-title":"J. Syst. Archit."},{"key":"e_1_2_6_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2017.2774252"},{"key":"e_1_2_6_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/43.822622"},{"issue":"4","key":"e_1_2_6_23_2","doi-asserted-by":"crossref","first-page":"467","DOI":"10.1049\/ip-cdt:20045016","article-title":"Topology adaptive network\u2010on\u2010chip design and implementation","volume":"152","author":"Bartic T.A.","year":"2005","journal-title":"IEE Proc., Comput. Digit. Tech."},{"key":"e_1_2_6_24_2","doi-asserted-by":"crossref","unstructured":"Bezerra G.B.P. Forrest S. Moses M. et al.: \u2018Modeling NoC traffic locality and energy consumption with rent's communication probability distribution\u2019.Proc. 12th ACM\/IEEE Int. Workshop on System Level Interconnect Prediction 2010","DOI":"10.1145\/1811100.1811103"},{"issue":"6","key":"e_1_2_6_25_2","doi-asserted-by":"crossref","first-page":"1403","DOI":"10.1109\/TGRS.2006.870433","article-title":"Synthesis, construction and validation of a fractal surface","volume":"44","author":"Ruello G.","year":"2006","journal-title":"IEEE Trans. Geosci. Remote Sens."},{"key":"e_1_2_6_26_2","unstructured":"Spip 6.6.1 image analyzer\u2019 2017"},{"key":"e_1_2_6_27_2","doi-asserted-by":"crossref","unstructured":"Radfar F. Zabihi M. Sarvari R.: \u2018Comparison between optimal interconnection network in different 2D and 3D NoC structures\u2019.27th IEEE Int. System\u2010on\u2010Chip Conf. (SOCC) 2014","DOI":"10.1109\/SOCC.2014.6948921"},{"key":"e_1_2_6_28_2","doi-asserted-by":"crossref","unstructured":"Balakrishnan A.: \u2018Analysis and optimization of global interconnects for many\u2010core architectures\u2019.Master of Science Georgia Institute of Technology 2010","DOI":"10.1109\/IITC.2010.5510317"},{"key":"e_1_2_6_29_2","unstructured":"Peh L.\u2010S. Dally W.J.: \u2018A delay model and speculative architecture for pipelined routers\u2019.Proc. Seventh Int. Symp. on High\u2010Performance Computer Architecture 2001"},{"key":"e_1_2_6_30_2","doi-asserted-by":"crossref","unstructured":"Kahng A.B. Bin L. Peh L.S. et al.: \u2018Orion 2.0: a fast and accurate NoC power and area model for early\u2010stage design space exploration\u2019.Design Automation and Test in Europe Conf. & Exhibition 2009","DOI":"10.1109\/DATE.2009.5090700"},{"key":"e_1_2_6_31_2","unstructured":"https:\/\/Networkonchip.Wordpress.Com\/2011\/02\/22\/Simulators\/ 2011"},{"key":"e_1_2_6_32_2","unstructured":"Kreutz M. Marcon C. Carro L. et al.: \u2018Energy and latency evaluation of NoC topologies\u2019.IEEE Int. Symp. on Circuits and Systems 2005"},{"key":"e_1_2_6_33_2","doi-asserted-by":"crossref","unstructured":"Bienia C. Kumar S. Singh J.P. et al.: \u2018The PARSEC benchmark suite: characterization and architectural implications\u2019.Proc. 17th Int. Conf. on Parallel Architectures and Compilation Techniques 2008","DOI":"10.1145\/1454115.1454128"},{"issue":"4","key":"e_1_2_6_34_2","doi-asserted-by":"crossref","first-page":"290","DOI":"10.1109\/LED.2010.2041319","article-title":"Optimal global interconnects for networks\u2010on\u2010chip in many\u2010core architectures","volume":"31","author":"Balakrishnan A.","year":"2010","journal-title":"IEEE Electron Device Lett."}],"container-title":["IET Computers & Digital Techniques"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1049\/iet-cdt.2018.5067","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/full-xml\/10.1049\/iet-cdt.2018.5067","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1049\/iet-cdt.2018.5067","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,2,6]],"date-time":"2021-02-06T01:08:09Z","timestamp":1612573689000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1049\/iet-cdt.2018.5067"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9,19]]},"references-count":33,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2019,1]]}},"alternative-id":["10.1049\/iet-cdt.2018.5067"],"URL":"https:\/\/doi.org\/10.1049\/iet-cdt.2018.5067","archive":["Portico"],"relation":{},"ISSN":["1751-8601","1751-861X"],"issn-type":[{"value":"1751-8601","type":"print"},{"value":"1751-861X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,9,19]]}}}