{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T13:10:04Z","timestamp":1648991404697},"reference-count":23,"publisher":"Elsevier BV","issue":"1-2","license":[{"start":{"date-parts":[[1998,5,1]],"date-time":"1998-05-01T00:00:00Z","timestamp":893980800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2013,7,17]],"date-time":"2013-07-17T00:00:00Z","timestamp":1374019200000},"content-version":"vor","delay-in-days":5556,"URL":"https:\/\/www.elsevier.com\/open-access\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Theoretical Computer Science"],"published-print":{"date-parts":[[1998,5]]},"DOI":"10.1016\/s0304-3975(97)00238-7","type":"journal-article","created":{"date-parts":[[2003,5,13]],"date-time":"2003-05-13T04:04:58Z","timestamp":1052798698000},"page":"171-188","source":"Crossref","is-referenced-by-count":6,"title":["Testing and reconfiguration of VLSI linear arrays"],"prefix":"10.1016","volume":"197","author":[{"given":"Roberta De","family":"Frisco","sequence":"first","affiliation":[]},{"given":"Angelo","family":"Monti","sequence":"additional","affiliation":[]},{"given":"Linda","family":"Pagli","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S0304-3975(97)00238-7_BIB1","series-title":"Proc. Internat. Conf. on Computer Design","first-page":"418","article-title":"Reconfiguration strategies in VLSI processor arrays","author":"Belkhale","year":"1988"},{"key":"10.1016\/S0304-3975(97)00238-7_BIB2","series-title":"4th IEEE Symp. on Parallel and Distributed Processing","first-page":"12","article-title":"Tolerating faults in a mesh with a row of spare nodes","author":"Bruck","year":"1992"},{"key":"10.1016\/S0304-3975(97)00238-7_BIB3","doi-asserted-by":"crossref","first-page":"55","DOI":"10.1109\/2.48799","article-title":"A taxonomy of reconfiguration techniques for fault-tolerant processor arrays","volume":"23","author":"Chean","year":"1990","journal-title":"IEEE Comput."},{"key":"10.1016\/S0304-3975(97)00238-7_BIB4","doi-asserted-by":"crossref","first-page":"105","DOI":"10.1016\/S0166-218X(96)00090-X","article-title":"Catastrophic faults in reconfigurable VLSI linear arrays","volume":"75","author":"De Prisco","year":"1997","journal-title":"Discrete Appl. Math."},{"key":"10.1016\/S0304-3975(97)00238-7_BIB5","series-title":"3rd Workshop on Algorithms and Data Structures","first-page":"553","article-title":"On reconfiguration of VLSI linear arrays","volume":"vol. 709","author":"De Prisco","year":"1993"},{"key":"10.1016\/S0304-3975(97)00238-7_BIB6","series-title":"Computers and Intractability","author":"Garey","year":"1979"},{"key":"10.1016\/S0304-3975(97)00238-7_BIB7","doi-asserted-by":"crossref","first-page":"694","DOI":"10.1145\/1634.2377","article-title":"Configuration of VLSI arrays in presence of defects","volume":"31","author":"Greene","year":"1984","journal-title":"J. ACM"},{"key":"10.1016\/S0304-3975(97)00238-7_BIB8","series-title":"Fundamentals of Computer Algorithms","author":"Horowitz","year":"1978"},{"key":"10.1016\/S0304-3975(97)00238-7_BIB9","doi-asserted-by":"crossref","first-page":"932","DOI":"10.1109\/12.30846","article-title":"On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors","volume":"38","author":"Hosseini","year":"1989","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0304-3975(97)00238-7_BIB10","series-title":"Proc. of 31st Annual Symp. on Foundation of Computer Science","first-page":"285","article-title":"Asymptotically tight bounds for computing with faulty arrays of processors","author":"Kaklamanis","year":"1990"},{"key":"10.1016\/S0304-3975(97)00238-7_BIB11","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1109\/MC.1982.1653825","article-title":"Why systolic architecture?","volume":"15","author":"Kung","year":"1982","journal-title":"IEEE Comput."},{"key":"10.1016\/S0304-3975(97)00238-7_BIB12","doi-asserted-by":"crossref","first-page":"163","DOI":"10.1016\/S0065-2458(08)60392-7","article-title":"Distributed Loop Computer Network","volume":"17","author":"Liu","year":"1978","journal-title":"Adv. Comput."},{"key":"10.1016\/S0304-3975(97)00238-7_BIB13","doi-asserted-by":"crossref","DOI":"10.22215\/etd\/1991-01969","article-title":"On reconfigurability of some regular architectures","author":"Nayak","year":"1991"},{"key":"10.1016\/S0304-3975(97)00238-7_BIB14","doi-asserted-by":"crossref","first-page":"133","DOI":"10.1016\/0167-9260(93)90049-I","article-title":"Efficient construction for VLSI reconfigurable arrays","volume":"15","author":"Nayak","year":"1993","journal-title":"Integration VLSI J."},{"key":"10.1016\/S0304-3975(97)00238-7_BIB15","series-title":"5th Internat. Parallel Processing Symp.","article-title":"Bounds on performance of VLSI processor arrays","author":"Nayak","year":"1991"},{"key":"10.1016\/S0304-3975(97)00238-7_BIB16","series-title":"Proc. 20th Internat. Symp. on Fault Tolerant Computing, FTCS'20","first-page":"202","article-title":"Fault-intolerance of reconfigurable systolic arrays","author":"Nayak","year":"1990"},{"key":"10.1016\/S0304-3975(97)00238-7_BIB17","doi-asserted-by":"crossref","first-page":"78","DOI":"10.1109\/MC.1986.1663151","article-title":"Fault-tolerance techniques for array structures used in supercomputing","volume":"19","author":"Negrini","year":"1986","journal-title":"IEEE Comput."},{"key":"10.1016\/S0304-3975(97)00238-7_BIB18","doi-asserted-by":"crossref","first-page":"337","DOI":"10.1016\/0020-0190(94)00047-6","article-title":"Counting the number of fault pattern in redundant VLSI arrays","volume":"50","author":"Pagli","year":"1994","journal-title":"Inform. Process. Lett."},{"key":"10.1016\/S0304-3975(97)00238-7_BIB19","volume":"vols. 1 and 2","year":"1986"},{"key":"10.1016\/S0304-3975(97)00238-7_BIB20","doi-asserted-by":"crossref","first-page":"568","DOI":"10.1109\/TC.1984.1676483","article-title":"Fault tolerance in binary tree architectures","volume":"C-33","author":"Raghavendra","year":"1984","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0304-3975(97)00238-7_BIB21","doi-asserted-by":"crossref","first-page":"902","DOI":"10.1109\/TC.1983.1676134","article-title":"The diogenes approach to testable fault-tolerant arrays of processors","volume":"32","author":"Rosemberg","year":"1983","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0304-3975(97)00238-7_BIB22","doi-asserted-by":"crossref","first-page":"480","DOI":"10.1109\/12.54841","article-title":"Efficient algorithms for reconfiguration in VLSI\/WSI arrays","volume":"39","author":"Roychowdhury","year":"1990","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0304-3975(97)00238-7_BIB23","first-page":"712","article-title":"Reconfigurable architectures for VLSI processing arrays","volume":"74","author":"Sami","year":"1986"}],"container-title":["Theoretical Computer Science"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0304397597002387?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0304397597002387?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2020,1,8]],"date-time":"2020-01-08T17:47:34Z","timestamp":1578505654000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0304397597002387"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,5]]},"references-count":23,"journal-issue":{"issue":"1-2","published-print":{"date-parts":[[1998,5]]}},"alternative-id":["S0304397597002387"],"URL":"https:\/\/doi.org\/10.1016\/s0304-3975(97)00238-7","relation":{},"ISSN":["0304-3975"],"issn-type":[{"value":"0304-3975","type":"print"}],"subject":[],"published":{"date-parts":[[1998,5]]}}}