{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,23]],"date-time":"2025-04-23T23:25:36Z","timestamp":1745450736648},"reference-count":30,"publisher":"Elsevier BV","issue":"12","license":[{"start":{"date-parts":[[2003,12,1]],"date-time":"2003-12-01T00:00:00Z","timestamp":1070236800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2003,12,1]],"date-time":"2003-12-01T00:00:00Z","timestamp":1070236800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"},{"start":{"date-parts":[[2003,12,1]],"date-time":"2003-12-01T00:00:00Z","timestamp":1070236800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-017"},{"start":{"date-parts":[[2003,12,1]],"date-time":"2003-12-01T00:00:00Z","timestamp":1070236800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"},{"start":{"date-parts":[[2003,12,1]],"date-time":"2003-12-01T00:00:00Z","timestamp":1070236800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-012"},{"start":{"date-parts":[[2003,12,1]],"date-time":"2003-12-01T00:00:00Z","timestamp":1070236800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2003,12,1]],"date-time":"2003-12-01T00:00:00Z","timestamp":1070236800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-004"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Microelectronics Journal"],"published-print":{"date-parts":[[2003,12]]},"DOI":"10.1016\/s0026-2692(03)00206-4","type":"journal-article","created":{"date-parts":[[2003,8,12]],"date-time":"2003-08-12T16:45:47Z","timestamp":1060706747000},"page":"1153-1165","update-policy":"http:\/\/dx.doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":79,"title":["HotSpot: a dynamic compact thermal model at the processor-architecture level"],"prefix":"10.1016","volume":"34","author":[{"given":"Mircea R.","family":"Stan","sequence":"first","affiliation":[]},{"given":"Kevin","family":"Skadron","sequence":"additional","affiliation":[]},{"given":"Marco","family":"Barcella","sequence":"additional","affiliation":[]},{"given":"Wei","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Karthik","family":"Sankaranarayanan","sequence":"additional","affiliation":[]},{"given":"Sivakumar","family":"Velusamy","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S0026-2692(03)00206-4_BIB1","series-title":"Dynamic thermal management for high-performance microprocessors","author":"Brooks","year":"2001"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB2","series-title":"in: Proceedings of the 33rd Annual IEEE\/ACM International Symposium on Microarchitecture","article-title":"A framework for dynamic energy efficiency and temperature management","author":"Huang","year":"2000"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB3","series-title":"Dynamically managing processor temperature and power","author":"Rohou","year":"1999"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB4","series-title":"Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management","author":"Skadron","year":"2002"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB5","doi-asserted-by":"crossref","first-page":"2820","DOI":"10.1109\/TMTT.2002.805142","article-title":"Global coupled EM-electrical-thermal simulation and experimental validation for a spatial power combining MMIC array","author":"Batty","year":"2002","journal-title":"IEEE Transactions on Microwave Theory and Techniques"},{"issue":"3","key":"10.1016\/S0026-2692(03)00206-4_BIB6","doi-asserted-by":"crossref","first-page":"250","DOI":"10.1109\/92.609867","article-title":"Fully coupled dynamic electro-thermal simulation","volume":"5","author":"Digele","year":"1997","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB7","series-title":"MONSTR: a complete thermal simulator of electronic systems","author":"Koval","year":"1994"},{"issue":"12","key":"10.1016\/S0026-2692(03)00206-4_BIB8","doi-asserted-by":"crossref","first-page":"1283","DOI":"10.1109\/4.262001","article-title":"Electrothermal simulation of integrated circuits","volume":"28","author":"Lee","year":"1993","journal-title":"IEEE Journal of Solid-State Circuits"},{"issue":"3","key":"10.1016\/S0026-2692(03)00206-4_BIB9","doi-asserted-by":"crossref","first-page":"283","DOI":"10.1109\/92.609871","article-title":"Realistic and efficient simulation of electro-thermal effects in VLSI circuits","volume":"5","author":"Sabry","year":"1997","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"issue":"3","key":"10.1016\/S0026-2692(03)00206-4_BIB10","doi-asserted-by":"crossref","first-page":"258","DOI":"10.1109\/92.609868","article-title":"Electro-thermal and logi-thermal simulation of VLSI designs","volume":"5","author":"Sz\u00e9kely","year":"1997","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB11","series-title":"IC map from digital and thermal simulations","author":"Torki","year":"2002"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB12","article-title":"Managing the impact of increasing microprocessor power consumption","author":"Gunther","year":"2001","journal-title":"Intel Technol J"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB13","series-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"Brooks","year":"2000"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB14","series-title":"Dynamic compact thermal models: An overview of current and potential advances","author":"Sabry","year":"2002"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB15","series-title":"The CRC Handbook of Thermal Engineering","first-page":"2.1","article-title":"Thermal management","author":"Krum","year":"2000"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB16","unstructured":"P. Shivakumar, N.P. Jouppi, Cacti 3.0: an integrated cache timing, power and area model, Technical Report, Compaq Western Research Laboratory, Feb., 2001."},{"issue":"2","key":"10.1016\/S0026-2692(03)00206-4_BIB17","doi-asserted-by":"crossref","first-page":"98","DOI":"10.1109\/4.68123","article-title":"An area model for on-chip memories and its application","volume":"26","author":"Mulder","year":"1991","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB18","series-title":"Digital Integrated Circuits: A Design Perspective","author":"Rabaey","year":"1995"},{"issue":"6","key":"10.1016\/S0026-2692(03)00206-4_BIB19","doi-asserted-by":"crossref","first-page":"697","DOI":"10.1109\/43.766722","article-title":"High-level area and power estimation for VLSI circuits","volume":"18","author":"Nemani","year":"1999","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB20","series-title":"in: Proccedings of the Design Automation Conference","article-title":"A new algorithm for floorplan design","author":"Wong","year":"1986"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB21","unstructured":"MIPS R10000 die photo, from website: CPU Info Center, http:\/\/bwrc.eecs.berkeley.edu\/CIC\/die_photos\/#mips."},{"key":"10.1016\/S0026-2692(03)00206-4_BIB22","unstructured":"Intel Pentium die photo, from website: CPU Info Center, http:\/\/bwrc.eecs.berkeley.edu\/CIC\/die_photos\/pentium.gif."},{"issue":"2","key":"10.1016\/S0026-2692(03)00206-4_BIB23","first-page":"104","article-title":"Circuit implementation of a 600 MHz superscalar RISC microprocessor","volume":"26","author":"Matson","year":"1998","journal-title":"Computer Design: VLSI in Computers and Processors"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB24","unstructured":"R. Mahajan, Thermal management of CPUs: a perspective on trends, needs and opportunities, keynote presentation at the 8th Int'l Workshop on THERMal INvestigations of ICs and Systems, Oct., 2002."},{"key":"10.1016\/S0026-2692(03)00206-4_BIB25","unstructured":"Standard Performance Evaluation Corporation, SPEC CPU2000 Benchmarks, http:\/\/www.specbench.org\/osg\/cpu2000."},{"key":"10.1016\/S0026-2692(03)00206-4_BIB26","unstructured":"Floworks: Fluid Flow Analysis for SolidWorks, NIKA GmbH. Website, http:\/\/www.floworks.com."},{"key":"10.1016\/S0026-2692(03)00206-4_BIB27","series-title":"Studies on the error resulting from neglecting nonlinearity effects in dynamic compact model generation","author":"Rencz","year":"2002"},{"issue":"4","key":"10.1016\/S0026-2692(03)00206-4_BIB28","doi-asserted-by":"crossref","first-page":"323","DOI":"10.1115\/1.1389846","article-title":"A scalable multi-functional thermal test chip family: design and evaluation","volume":"123","author":"Benedek","year":"2001","journal-title":"Transactions of the ASME, Journal of Electronic Packaging"},{"key":"10.1016\/S0026-2692(03)00206-4_BIB29","unstructured":"M. McManus, S. Kasapi, PICA watches chips work, Optoelectronics World."},{"key":"10.1016\/S0026-2692(03)00206-4_BIB30","series-title":"Comparison of state-preserving vs. non-state preserving leakage control in caches","author":"Parikh","year":"2003"}],"container-title":["Microelectronics Journal"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0026269203002064?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0026269203002064?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2024,7,5]],"date-time":"2024-07-05T18:16:07Z","timestamp":1720203367000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0026269203002064"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,12]]},"references-count":30,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2003,12]]}},"alternative-id":["S0026269203002064"],"URL":"https:\/\/doi.org\/10.1016\/s0026-2692(03)00206-4","relation":{},"ISSN":["1879-2391"],"issn-type":[{"value":"1879-2391","type":"print"}],"subject":[],"published":{"date-parts":[[2003,12]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"HotSpot: a dynamic compact thermal model at the processor-architecture level","name":"articletitle","label":"Article Title"},{"value":"Microelectronics Journal","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/S0026-2692(03)00206-4","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"converted-article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 2003 Elsevier Science Ltd. All rights are reserved, including those for text and data mining, AI training, and similar technologies.","name":"copyright","label":"Copyright"}]}}