{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,9]],"date-time":"2024-07-09T06:41:49Z","timestamp":1720507309446},"reference-count":30,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T00:00:00Z","timestamp":1535760000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Integration"],"published-print":{"date-parts":[[2018,9]]},"DOI":"10.1016\/j.vlsi.2018.04.008","type":"journal-article","created":{"date-parts":[[2018,6,29]],"date-time":"2018-06-29T01:23:16Z","timestamp":1530235396000},"page":"220-231","update-policy":"http:\/\/dx.doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":2,"special_numbering":"C","title":["Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling"],"prefix":"10.1016","volume":"63","author":[{"given":"Roberto G.","family":"Rizzo","sequence":"first","affiliation":[]},{"given":"Andrea","family":"Calimera","sequence":"additional","affiliation":[]},{"given":"Jun","family":"Zhou","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/j.vlsi.2018.04.008_bib1","series-title":"Proceedings 13th International Symposium on System Synthesis","first-page":"25","article-title":"Battery-driven dynamic power management of portable systems","author":"Benini","year":"2000"},{"key":"10.1016\/j.vlsi.2018.04.008_bib2","series-title":"2011 Design, Automation Test in Europe","first-page":"1","article-title":"Adaptive Voltage Over-Scaling for resilient applications","author":"Krause","year":"2011"},{"key":"10.1016\/j.vlsi.2018.04.008_bib3","series-title":"IFIP\/IEEE International Conference on Very Large Scale Integration-system on a Chip","first-page":"152","article-title":"Beyond ideal DVFS through ultra-fine grain vdd-hopping","author":"Peluso","year":"2016"},{"issue":"6","key":"10.1016\/j.vlsi.2018.04.008_bib4","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/MM.2004.85","article-title":"Razor: circuit-level correction of timing errors for low-power operation","volume":"24","author":"Ernst","year":"2004","journal-title":"IEEE Micro"},{"key":"10.1016\/j.vlsi.2018.04.008_bib5","series-title":"Microarchitecture, 2003. MICRO-36. Proceedings. 36th Annual IEEE\/ACM International Symposium on","first-page":"7","article-title":"Razor: a low-power pipeline based on circuit-level timing speculation","author":"Ernst","year":"2003"},{"issue":"4","key":"10.1016\/j.vlsi.2018.04.008_bib6","doi-asserted-by":"crossref","first-page":"792","DOI":"10.1109\/JSSC.2006.870912","article-title":"A self-tuning dvs processor using delay-error detection and correction","volume":"41","author":"Das","year":"2006","journal-title":"IEEE J. Solid State Circ."},{"issue":"1","key":"10.1016\/j.vlsi.2018.04.008_bib7","doi-asserted-by":"crossref","first-page":"32","DOI":"10.1109\/JSSC.2008.2007145","article-title":"RazorII: in situ error detection and correction for pvt and ser tolerance","volume":"44","author":"Das","year":"2009","journal-title":"IEEE J. Solid State Circ."},{"key":"10.1016\/j.vlsi.2018.04.008_bib8","series-title":"On-line Testing Symposium (IOLTS), 2010 IEEE 16th International","first-page":"283","article-title":"Timing error tolerance in nanometer ICs","author":"Valadimas","year":"2010"},{"key":"10.1016\/j.vlsi.2018.04.008_bib9","series-title":"International Conference on Very Large Scale Integration (VLSI-SoC), 2017 IEEE 25th International","article-title":"Early bird sampling: a short-paths free error detection-correction strategy for data-driven VOS","author":"Rizzo","year":"2017"},{"key":"10.1016\/j.vlsi.2018.04.008_bib10","series-title":"Circuit Theory and Design (ECCTD), 2011 20th European Conference on","first-page":"548","article-title":"Voltage over-scaling: a cross-layer design perspective for energy efficient systems","author":"Karakonstantis","year":"2011"},{"issue":"1","key":"10.1016\/j.vlsi.2018.04.008_bib11","doi-asserted-by":"crossref","first-page":"49","DOI":"10.1109\/JSSC.2008.2007148","article-title":"Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance","volume":"44","author":"Bowman","year":"2009","journal-title":"IEEE J. Solid State Circ."},{"issue":"1","key":"10.1016\/j.vlsi.2018.04.008_bib12","doi-asserted-by":"crossref","first-page":"194","DOI":"10.1109\/JSSC.2010.2089657","article-title":"A 45 nm resilient microprocessor core for dynamic variation tolerance","volume":"46","author":"Bowman","year":"2011","journal-title":"IEEE J. Solid State Circ."},{"issue":"11","key":"10.1016\/j.vlsi.2018.04.008_bib13","doi-asserted-by":"crossref","first-page":"1947","DOI":"10.1109\/TCAD.2007.896305","article-title":"Crista: a new paradigm for low-power, variation-tolerant, and adaptive circuit synthesis using critical path isolation","volume":"26","author":"Ghosh","year":"2007","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circ. Syst."},{"key":"10.1016\/j.vlsi.2018.04.008_bib14","series-title":"Proceedings of the 2007 International Symposium on Low Power Electronics and Design","first-page":"74","article-title":"Low-power process-variation tolerant arithmetic units using input-based elastic clocking","author":"Mohapatra","year":"2007"},{"issue":"10","key":"10.1016\/j.vlsi.2018.04.008_bib15","doi-asserted-by":"crossref","first-page":"1437","DOI":"10.1109\/TCAD.2009.2030436","article-title":"Elastic circuits","volume":"28","author":"Carmona","year":"2009","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circ. Syst."},{"issue":"5","key":"10.1016\/j.vlsi.2018.04.008_bib16","doi-asserted-by":"crossref","first-page":"497","DOI":"10.1109\/TVLSI.2004.826201","article-title":"Reliable low-power digital signal processing via reduced precision redundancy","volume":"12","author":"Shim","year":"2004","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"10.1016\/j.vlsi.2018.04.008_bib17","series-title":"Computer Design (ICCD), 2015 33rd IEEE International Conference on","first-page":"86","article-title":"An automated design flow for approximate circuits based on reduced precision redundancy","author":"Pagliari","year":"2015"},{"key":"10.1016\/j.vlsi.2018.04.008_bib18","series-title":"Proceedings of the 2010 Asia and South Pacific Design Automation Conference","first-page":"825","article-title":"Slack redistribution for graceful degradation under voltage overscaling","author":"Kahng","year":"2010"},{"issue":"11","key":"10.1016\/j.vlsi.2018.04.008_bib19","doi-asserted-by":"crossref","first-page":"1608","DOI":"10.1109\/TVLSI.2009.2025884","article-title":"Temperature-insensitive dual- vrmth synthesis for nanometer cmos technologies under inverse temperature dependence","volume":"18","author":"Calimera","year":"2010","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"10.1016\/j.vlsi.2018.04.008_bib20","series-title":"Proceedings of the 43rd Annual Design Automation Conference","first-page":"1047","article-title":"Modeling and minimization of pmos nbti effect for robust nanometer design","author":"Vattikonda","year":"2006"},{"key":"10.1016\/j.vlsi.2018.04.008_bib21","series-title":"New Generation of Circuits and Systems Conference (NGCAS), 2017 IEEE 1st International","article-title":"Tunable error detection-correction fo efficient voltage over-scaling","author":"Rizzo","year":"2017"},{"issue":"6","key":"10.1016\/j.vlsi.2018.04.008_bib22","doi-asserted-by":"crossref","first-page":"1478","DOI":"10.1109\/JSSC.2015.2418713","article-title":"Variation-tolerant, ultra-low-voltage microprocessor with a low-overhead, within-a-cycle in-situ timing-error detection and correction technique","volume":"50","author":"Kim","year":"2015","journal-title":"IEEE J. Solid State Circ."},{"issue":"9","key":"10.1016\/j.vlsi.2018.04.008_bib23","doi-asserted-by":"crossref","first-page":"2054","DOI":"10.1109\/JSSC.2014.2328658","article-title":"Razor-lite: a light-weight register for error detection by observing virtual supply rails","volume":"49","author":"Kwon","year":"2014","journal-title":"IEEE J. Solid State Circ."},{"issue":"4","key":"10.1016\/j.vlsi.2018.04.008_bib24","doi-asserted-by":"crossref","first-page":"558","DOI":"10.1109\/TCAD.2014.2304681","article-title":"Pushpull: short-path padding for timing error resilient circuits","volume":"33","author":"Yang","year":"2014","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circ. Syst."},{"issue":"8","key":"10.1016\/j.vlsi.2018.04.008_bib25","doi-asserted-by":"crossref","first-page":"2290","DOI":"10.1109\/TCSI.2014.2333332","article-title":"A 1 GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation","volume":"61","author":"Das","year":"2014","journal-title":"IEEE Trans. Circ. Syst. I Regul. Pap."},{"issue":"1","key":"10.1016\/j.vlsi.2018.04.008_bib26","doi-asserted-by":"crossref","first-page":"66","DOI":"10.1109\/JSSC.2012.2220912","article-title":"Bubble razor: eliminating timing margins in an arm cortex-m3 processor in 45 nm cmos using architecturally independent error detection and correction","volume":"48","author":"Fojtik","year":"2013","journal-title":"IEEE J. Solid State Circ."},{"issue":"1","key":"10.1016\/j.vlsi.2018.04.008_bib27","doi-asserted-by":"crossref","first-page":"49","DOI":"10.1109\/JSSC.2008.2007148","article-title":"Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance","volume":"44","author":"Bowman","year":"2009","journal-title":"IEEE J. Solid State Circ."},{"key":"10.1016\/j.vlsi.2018.04.008_bib28","series-title":"Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian","first-page":"129","article-title":"Hepp: a new in-situ timing-error prediction and prevention technique for variation-tolerant ultra-low-voltage designs","author":"Zhou","year":"2013"},{"issue":"6","key":"10.1016\/j.vlsi.2018.04.008_bib29","doi-asserted-by":"crossref","first-page":"639","DOI":"10.1109\/TVLSI.2008.2000248","article-title":"Dynamic thermal clock skew compensation using tunable delay buffers","volume":"16","author":"Chakraborty","year":"2008","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"10.1016\/j.vlsi.2018.04.008_bib30","series-title":"Proceedings of the 17th ACM Great Lakes Symposium on VLSI","first-page":"501","article-title":"Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology","author":"Calimera","year":"2007"}],"updated-by":[{"updated":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"DOI":"10.1016\/j.vlsi.2019.11.011","type":"erratum","label":"Erratum"}],"container-title":["Integration"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167926017307915?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167926017307915?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2018,10,17]],"date-time":"2018-10-17T16:25:49Z","timestamp":1539793549000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0167926017307915"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9]]},"references-count":30,"alternative-id":["S0167926017307915"],"URL":"https:\/\/doi.org\/10.1016\/j.vlsi.2018.04.008","relation":{},"ISSN":["0167-9260"],"issn-type":[{"value":"0167-9260","type":"print"}],"subject":[],"published":{"date-parts":[[2018,9]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling","name":"articletitle","label":"Article Title"},{"value":"Integration","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.vlsi.2018.04.008","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2018 Elsevier B.V. All rights reserved.","name":"copyright","label":"Copyright"}]}}