乐胖代购免代理版

{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,8,29]],"date-time":"2023-08-29T04:53:40Z","timestamp":1693284820493},"reference-count":50,"publisher":"Elsevier BV","issue":"3-4","license":[{"start":{"date-parts":[[2015,3,1]],"date-time":"2015-03-01T00:00:00Z","timestamp":1425168000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2015,3]]},"DOI":"10.1016\/j.sysarc.2015.03.001","type":"journal-article","created":{"date-parts":[[2015,4,9]],"date-time":"2015-04-09T05:30:33Z","timestamp":1428557433000},"page":"157-171","update-policy":"http:\/\/dx.doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":4,"title":["MaCACH: An adaptive cache-aware hybrid FTL mapping scheme using feedback control for efficient page-mapped space management"],"prefix":"10.1016","volume":"61","author":[{"given":"Jalil","family":"Boukhobza","sequence":"first","affiliation":[]},{"given":"Pierre","family":"Olivier","sequence":"additional","affiliation":[]},{"given":"St\u00e9phane","family":"Rubini","sequence":"additional","affiliation":[]},{"given":"Laurent","family":"Lemarchand","sequence":"additional","affiliation":[]},{"given":"Yassine","family":"Hadjadj-Aoul","sequence":"additional","affiliation":[]},{"given":"Arezki","family":"Laga","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"issue":"1","key":"10.1016\/j.sysarc.2015.03.001_b0005","doi-asserted-by":"crossref","first-page":"39","DOI":"10.1109\/MC.2011.18","article-title":"From microprocessors to nanostores: rethinking data-centric systems","volume":"44","author":"Ranganathan","year":"2011","journal-title":"Computer"},{"issue":"4","key":"10.1016\/j.sysarc.2015.03.001_b0010","doi-asserted-by":"crossref","first-page":"2005","DOI":"10.1109\/TCE.2009.5373762","article-title":"HFTL: hybrid flash translation layer based on hot data identification for flash memory","volume":"55","author":"Lee","year":"2009","journal-title":"IEEE Trans. Consumer Electron."},{"key":"10.1016\/j.sysarc.2015.03.001_b0015","unstructured":"Q. Wei, B. Gong, S. Pathak, B. Veeravalli, L. Zeng, K. Okada, WAFTL: a workload adaptive flash translation layer with data partition, in\u201d Proceedings of 27th IEEE Symposium on Mass Storage Systems and Technologies (MSST), May 2011."},{"key":"10.1016\/j.sysarc.2015.03.001_b0020","doi-asserted-by":"crossref","unstructured":"D. Park, B. Debnath, D. Du, A workload-aware adaptive hybrid flash translation layer with an efficient caching strategy, in: proceedings of the IEEE International Symposium on of Modeling, Analysis & Simulation of Computer and Telecommunication Systems (MASCOTS), July 2011.","DOI":"10.1109\/MASCOTS.2011.29"},{"key":"10.1016\/j.sysarc.2015.03.001_b0025","doi-asserted-by":"crossref","unstructured":"S. Park, J. Park, S. Kim. C.C. Weems, A pattern adaptive NAND flash memory storage structure, IEEE Trans. Computers, 61 (1) (2012) 134\u2013138.","DOI":"10.1109\/TC.2010.212"},{"key":"10.1016\/j.sysarc.2015.03.001_b0030","doi-asserted-by":"crossref","unstructured":"C. Wang, W. Wong, ADAPT: efficient workload-sensitive flash management based on adaptation, prediction and aggregation, in: Mass Storage Systems and Technologies (MSST), 2012 IEEE 28th Symposium on April 2012.","DOI":"10.1109\/MSST.2012.6232388"},{"key":"10.1016\/j.sysarc.2015.03.001_b0035","doi-asserted-by":"crossref","unstructured":"H. Kwon, E. Kim, J. Choi, D. Lee, S.H. Noh. Janus-FTL: finding the optimal point on the spectrum between page and block mapping schemes, in: Proceedings of the tenth ACM international conference on Embedded software (EMSOFT\u201910), October 2010.","DOI":"10.1145\/1879021.1879044"},{"key":"10.1016\/j.sysarc.2015.03.001_b0040","doi-asserted-by":"crossref","unstructured":"D. Liu, T. Wang, Y. Wang, Z. Qin, Z. Shao, PCM-FTL: A write-activity-aware nand flash memory management scheme for PCM-based embedded systems, in: IEEE 32nd Real-Time Systems Symposium (RTSS), December 2011.","DOI":"10.1109\/RTSS.2011.40"},{"issue":"2","key":"10.1016\/j.sysarc.2015.03.001_b0045","doi-asserted-by":"crossref","first-page":"485","DOI":"10.1109\/TCE.2006.1649669","article-title":"FAB: flash-aware buffer management policy for portable media players","volume":"52","author":"Jo","year":"2006","journal-title":"IEEE Trans. Cons. Electron."},{"issue":"6","key":"10.1016\/j.sysarc.2015.03.001_b0050","doi-asserted-by":"crossref","first-page":"744","DOI":"10.1109\/TC.2008.224","article-title":"Performance trade-offs in using NVRAM write buffer for flash memory-based storage devices","volume":"58","author":"Kang","year":"2009","journal-title":"IEEE Trans. Comp."},{"key":"10.1016\/j.sysarc.2015.03.001_b0055","unstructured":"H. Kim, S. Ahn, BPLRU: a buffer management scheme for improving random writes in flash storage, in: Proceedings of the 6th USENIX Conference on File and Storage Technologies (FAST), February 2008."},{"key":"10.1016\/j.sysarc.2015.03.001_b0060","doi-asserted-by":"crossref","unstructured":"G. Wu, B. Eckart, X. He, BPAC: an adaptive write buffer management scheme for flash-based solid state drives, in: Proceedings of 26th IEEE Symposium on Mass Storage Systems and Technologies (MSST), May 2010.","DOI":"10.1109\/MSST.2010.5496998"},{"key":"10.1016\/j.sysarc.2015.03.001_b0065","doi-asserted-by":"crossref","unstructured":"B. Debnath, S. Subramanya, D. Du, D. J. Lilja, Large block CLOCK (LB-CLOCK): a write caching algorithm for solid state disks, in: Proceedings of the IEEE International Symposium on Modeling, Analysis & Simulation of Computer and Telecommunication Systems (MASCOTS), September 2009.","DOI":"10.1109\/MASCOT.2009.5366737"},{"key":"10.1016\/j.sysarc.2015.03.001_b0070","doi-asserted-by":"crossref","unstructured":"J. Hu, H. Jiang, T. Tian, L. Xu, PUD-LRU: an erase-efficient write buffer management algorithm for flash memory SSD, in: Proceedings of the IEEE International Symposium on of Modeling, Analysis & Simulation of Computer and Telecommunication Systems (MASCOTS), August 2010.","DOI":"10.1109\/MASCOTS.2010.16"},{"issue":"3","key":"10.1016\/j.sysarc.2015.03.001_b0075","doi-asserted-by":"crossref","first-page":"1228","DOI":"10.1109\/TCE.2008.4637611","article-title":"Recently-evicted-first buffer replacement policy for flash storage devices","volume":"54","author":"Seo","year":"2008","journal-title":"IEEE Trans. Cons. Electron."},{"key":"10.1016\/j.sysarc.2015.03.001_b0080","unstructured":"J. Boukhobza, P. Olivier, S. Rubini, A cache management strategy to replace wear leveling techniques for embedded flash memory, in: International Symposium on Performance Evaluation of Computer & Telecommunication Systems (SPECTS), June 2011."},{"issue":"4","key":"10.1016\/j.sysarc.2015.03.001_b0085","doi-asserted-by":"crossref","first-page":"1765","DOI":"10.1109\/TCE.2011.6131152","article-title":"Bridging the information gap between buffer and flash translation layer for flash memory","volume":"57","author":"Liao","year":"2011","journal-title":"IEEE Trans. Cons. Electron."},{"key":"10.1016\/j.sysarc.2015.03.001_b0090","doi-asserted-by":"crossref","unstructured":"J. Boukhobza, P. Olivier, S. Rubini, CACH-FTL: a cache-aware configurable hybrid flash translation layer, in: 2013 21st Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), March 2013.","DOI":"10.1109\/PDP.2013.71"},{"key":"10.1016\/j.sysarc.2015.03.001_b0095","series-title":"Nonvolatile Memory Technologies with Emphasis on Flash","author":"Brewer","year":"2008"},{"key":"10.1016\/j.sysarc.2015.03.001_b0100","unstructured":"A. Ban, Flash File System Optimized for Page-Mode Flash Technologies, United States Patent, No 5,937,425, 1999."},{"key":"10.1016\/j.sysarc.2015.03.001_b0105","doi-asserted-by":"crossref","unstructured":"C. Wu, T. Kuo, An adaptive two-level management for the flash translation layer in embedded systems, in: Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), November 2006.","DOI":"10.1109\/ICCAD.2006.320107"},{"issue":"11","key":"10.1016\/j.sysarc.2015.03.001_b0110","doi-asserted-by":"crossref","first-page":"1571","DOI":"10.1109\/TC.2008.61","article-title":"Configurable flash-memory management: performance versus overheads","volume":"57","author":"Hsieh","year":"2008","journal-title":"IEEE Trans. Comp."},{"key":"10.1016\/j.sysarc.2015.03.001_b0115","doi-asserted-by":"crossref","unstructured":"J. Kim, J.M. Kim, S.H. Noh, S.L. Min, Y. Cho, A space-efficient flash translation layer for compactflash systems, IEEE Trans. Cons. Electron. 48 (2) (2002) 366\u2013375.","DOI":"10.1109\/TCE.2002.1010143"},{"key":"10.1016\/j.sysarc.2015.03.001_b0120","doi-asserted-by":"crossref","unstructured":"Y. Wang, D. Liu, M. Wang, Z. Qin, Y. Guan, RNFTL: a reuse-aware NAND flash translation layer for flash memory, in: Proceedings of the ACM SIGPLAN\/SIGBED Conference on LANGUAGES, Compilers, and Tools for Embedded Systems (LCTES), April 2010.","DOI":"10.1145\/1755888.1755912"},{"issue":"3","key":"10.1016\/j.sysarc.2015.03.001_b0125","first-page":"1","article-title":"A log buffer based flash translation layer using fully associative sector translation","volume":"6","author":"Lee","year":"2007","journal-title":"ACM Trans. Embedded Computing Sys."},{"key":"10.1016\/j.sysarc.2015.03.001_b0130","unstructured":"H. Cho, D. Shin, Y.I. Eom, KAST: K-associative sector translation for NAND flash memory in real-time systems, in: Proceedings of Design, Automation and Test in Europe (DATE), April 2009."},{"issue":"6","key":"10.1016\/j.sysarc.2015.03.001_b0135","doi-asserted-by":"crossref","first-page":"36","DOI":"10.1145\/1453775.1453783","article-title":"LAST: locality aware sector translation for NAND flash memory based storage systems","volume":"42","author":"Lee","year":"2008","journal-title":"ACM SIGOPS Oper. Syst. Rev."},{"key":"10.1016\/j.sysarc.2015.03.001_b0140","doi-asserted-by":"crossref","unstructured":"Y. Guan, G. Wang, Y. Wang, R. Chen, Z. Shao, Block-level Log-block Management for NAND Flash Memory Storage Systems, in: Proceedings of the ACM SIGPLAN\/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), June 2013.","DOI":"10.1145\/2491899.2465560"},{"key":"10.1016\/j.sysarc.2015.03.001_b0145","doi-asserted-by":"crossref","unstructured":"C. Wang, W. Wong, TreeFTL: efficient RAM management for high performance of NAND flash-based storage systems, in: Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013.","DOI":"10.7873\/DATE.2013.086"},{"key":"10.1016\/j.sysarc.2015.03.001_b0150","doi-asserted-by":"crossref","unstructured":"Z Qin, Y. Wang, D. Liu, Z. Shao, Y. Guan, MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems, in: Proceedings of the 48th Design Automation Conference (DAC\u201911), 2011.","DOI":"10.1145\/2024724.2024730"},{"key":"10.1016\/j.sysarc.2015.03.001_b0155","doi-asserted-by":"crossref","unstructured":"P. Huang, Y. Chang, T. Kuo. Joint management of RAM and flash memory with access pattern considerations, in: Proceedings of ACM\/EDAC\/IEEE Design Automation Conference (DAC), 2012.","DOI":"10.1145\/2228360.2228518"},{"key":"10.1016\/j.sysarc.2015.03.001_b0160","unstructured":"X. Hu, R. Haas, The Fundamental Limit of Flash Random Write Performance: Understanding, Analysis and Performance Modelling, Research Report RZ 3771 IBM, Switzerland, 2010."},{"key":"10.1016\/j.sysarc.2015.03.001_b0165","doi-asserted-by":"crossref","unstructured":"S. Park, J. Cha, S. Kang, Integrated write buffer management for solid state drives, J. Syst. Archit. 60 (4) (2014) 329\u2013344.","DOI":"10.1016\/j.sysarc.2014.01.005"},{"key":"10.1016\/j.sysarc.2015.03.001_b0170","doi-asserted-by":"crossref","unstructured":"L. Chang; Y. Su, Plugging versus logging: a new approach to write buffer management for solid-state disks, in: 48th ACM\/EDAC\/IEEE Design Automation Conference (DAC), June 2011.","DOI":"10.1145\/2024724.2024731"},{"key":"10.1016\/j.sysarc.2015.03.001_b0175","doi-asserted-by":"crossref","unstructured":"T. Wang, D. Liu, Y. Wang, Z. Shao, FTL2: a hybrid flash translation layer with logging for write reduction in flash memory, in: Proceedings of the ACM SIGPLAN\/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), June 2013.","DOI":"10.1145\/2491899.2465563"},{"key":"10.1016\/j.sysarc.2015.03.001_b0180","doi-asserted-by":"crossref","unstructured":"A. Gupta, Y. Kim, B. Urgaonkar, DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings, in: Proceedings of the 14th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS\u201909), New York, 2009.","DOI":"10.1145\/1508244.1508271"},{"key":"10.1016\/j.sysarc.2015.03.001_b0185","unstructured":"K.J. Astrom, T. Hagglund, Advanced PID Control. ISA-The Instrumentation, Systems, and Automation Society, ISBN 1556179421, 2006."},{"key":"10.1016\/j.sysarc.2015.03.001_b0190","doi-asserted-by":"crossref","unstructured":"X. Hu, E. Eleftheriou, R. Haas, I. Iliadis, R. Pletka, Write amplification analysis in fash-based solid state drives, in: Proceedings of the ACM System and Storage Conference (SYSTOR), 2009.","DOI":"10.1145\/1534530.1534544"},{"issue":"1","key":"10.1016\/j.sysarc.2015.03.001_b0195","first-page":"3","article-title":"A survey of PID auto-tuning methods: feature issue controller tuning","volume":"38","author":"Gorez","year":"1997","journal-title":"Journal A"},{"issue":"6","key":"10.1016\/j.sysarc.2015.03.001_b0200","doi-asserted-by":"crossref","first-page":"753","DOI":"10.1109\/TC.2011.67","article-title":"ROSE: a novel flash translation layer for NAND flash memory based on hybrid address translation","volume":"60","author":"Chiao","year":"2011","journal-title":"IEEE Trans. Comp."},{"key":"10.1016\/j.sysarc.2015.03.001_b0205","doi-asserted-by":"crossref","unstructured":"Y. Kim, B. Taurus, A. Gupta, B. Urgaonkar, FlashSim: a simulator for NAND flash-based solid-state drives, in: Proceedings of the 1st International Conference on Advances in System Simulation (SIMUL), September 2009.","DOI":"10.1109\/SIMUL.2009.17"},{"key":"10.1016\/j.sysarc.2015.03.001_b0210","unstructured":"G. R. Ganger, B. Worthington, Y.N. Patt, The Disksim Simulation Environment Version 3.0 Reference Manual, Tech. Report CMU-CS-03-102, Pittsburgh, 2003."},{"key":"10.1016\/j.sysarc.2015.03.001_b0215","unstructured":"N. Agrawal, V. Prabhakaran, T. Wobber, J.D. Davis, M. Manasse, R. Panigrahy, Design tradeoffs for SSD performance, in: Proceedings of the USENIX Annual Technical Conference (ATC), June 2008."},{"key":"10.1016\/j.sysarc.2015.03.001_b0220","unstructured":"OLTP Traces - UMass trace repository, (accessed 02.02.14)."},{"key":"10.1016\/j.sysarc.2015.03.001_b0225","unstructured":"Cello99 Traces, HP Labs. (accessed on 02.02.14)."},{"key":"10.1016\/j.sysarc.2015.03.001_b0230","doi-asserted-by":"crossref","unstructured":"D. Narayanan, A. Donnelly, A. Rowstron, Write off-loading: practical power management for enterprise storage, in: Proceedings of the 6th USENIX Conference on File and Storage Technologies (FAST), 2008.","DOI":"10.1145\/1416944.1416949"},{"issue":"1","key":"10.1016\/j.sysarc.2015.03.001_b0235","doi-asserted-by":"crossref","first-page":"36","DOI":"10.3390\/computers3010036","article-title":"A scalable and highly configurable cache-aware hybrid flash translation layer","volume":"3","author":"Boukhobza","year":"2014","journal-title":"Computers"},{"key":"10.1016\/j.sysarc.2015.03.001_b0240","unstructured":"S-W. Lee, J-S. Kim, Understanding SSDs with the OpenSSD Platform, Flash Summit, USA, 2011."},{"key":"10.1016\/j.sysarc.2015.03.001_b0245","doi-asserted-by":"crossref","unstructured":"J. Knowles, D. Corne, Approximating the nondominated front using the Pareto archived evolution strategy, Evol. Comput. 8 (2) (2000) 149\u2013172, MIT press.","DOI":"10.1162\/106365600568167"},{"key":"10.1016\/j.sysarc.2015.03.001_b0250","doi-asserted-by":"crossref","unstructured":"C. Fonseca, P. Fleming, An overview of evolutionary algorithms in multiobjective optimization, Evol. Comput. 3 (1) (1995) 1\u201316, MIT Press.","DOI":"10.1162\/evco.1995.3.1.1"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762115000156?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762115000156?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,8,23]],"date-time":"2019-08-23T01:14:45Z","timestamp":1566522885000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762115000156"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,3]]},"references-count":50,"journal-issue":{"issue":"3-4","published-print":{"date-parts":[[2015,3]]}},"alternative-id":["S1383762115000156"],"URL":"https:\/\/doi.org\/10.1016\/j.sysarc.2015.03.001","relation":{},"ISSN":["1383-7621"],"issn-type":[{"value":"1383-7621","type":"print"}],"subject":[],"published":{"date-parts":[[2015,3]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"MaCACH: An adaptive cache-aware hybrid FTL mapping scheme using feedback control for efficient page-mapped space management","name":"articletitle","label":"Article Title"},{"value":"Journal of Systems Architecture","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.sysarc.2015.03.001","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 2015 Elsevier B.V. All rights reserved.","name":"copyright","label":"Copyright"}]}}