乐胖代购免代理版

{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T18:38:58Z","timestamp":1648838338835},"reference-count":26,"publisher":"Elsevier BV","issue":"1-3","license":[{"start":{"date-parts":[[2010,12,1]],"date-time":"2010-12-01T00:00:00Z","timestamp":1291161600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Neurocomputing"],"published-print":{"date-parts":[[2010,12]]},"DOI":"10.1016\/j.neucom.2010.03.005","type":"journal-article","created":{"date-parts":[[2010,3,30]],"date-time":"2010-03-30T17:46:45Z","timestamp":1269971205000},"page":"291-300","source":"Crossref","is-referenced-by-count":0,"title":["Techniques for power reduction in an SIMD implementation of the VQ\/SOM algorithms"],"prefix":"10.1016","volume":"74","author":[{"given":"D.C.","family":"Hendry","sequence":"first","affiliation":[]},{"given":"R.","family":"Cambio","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/j.neucom.2010.03.005_bib1","series-title":"Vector Quantization and Signal Compression","author":"Gersho","year":"1992"},{"key":"10.1016\/j.neucom.2010.03.005_bib2","series-title":"Self-Organizing Maps, Springer Series in Information Sciences","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-642-56927-2","author":"Kohonen","year":"2001"},{"issue":"5","key":"10.1016\/j.neucom.2010.03.005_bib3","doi-asserted-by":"crossref","first-page":"726","DOI":"10.1109\/JSSC.2003.810064","article-title":"A still-image encoder based on adaptive resolution vector quantization featuring needless calculation elimination architecture","volume":"38","author":"Fujibayashi","year":"2003","journal-title":"IEEE Journal of Solid"},{"issue":"5","key":"10.1016\/j.neucom.2010.03.005_bib4","doi-asserted-by":"crossref","first-page":"1085","DOI":"10.1109\/TNN.2003.816353","article-title":"Ip core implementation of a self-organising neural network","volume":"14","author":"Hendry","year":"2003","journal-title":"IEEE Transactions on Neural Networks"},{"issue":"21","key":"10.1016\/j.neucom.2010.03.005_bib5","doi-asserted-by":"crossref","first-page":"1524","DOI":"10.1049\/el:20030961","article-title":"Reduced power som\/lvq arrays through distance thresholding","volume":"39","author":"Hendry","year":"2003","journal-title":"Electronics Letters"},{"key":"10.1016\/j.neucom.2010.03.005_bib6","doi-asserted-by":"crossref","unstructured":"C. Aggarwal, A. Hinneburg, D. Keim, On the Surprising Behaviour of Distance Metrics in High Dimensional Space, in: Database Theory\u2014ICDT 2001, Lecture Notes in Computer Science, Springer, 2001, vol. 1973, pp. 420\u2013434.","DOI":"10.1007\/3-540-44503-X_27"},{"issue":"1\u20133","key":"10.1016\/j.neucom.2010.03.005_bib7","doi-asserted-by":"crossref","first-page":"31","DOI":"10.1016\/S0925-2312(98)00042-3","article-title":"Som accelerator systems","volume":"21","author":"Ruping","year":"1998","journal-title":"Neurocomputing"},{"issue":"10","key":"10.1016\/j.neucom.2010.03.005_bib8","doi-asserted-by":"crossref","first-page":"983","DOI":"10.1016\/j.sysarc.2008.04.007","article-title":"A novel hardware-oriented kohonen som image compression algorithm and its fpga implementation","volume":"54","author":"Kurdthongmee","year":"2008","journal-title":"Journal of Systems Architecture"},{"issue":"11","key":"10.1016\/j.neucom.2010.03.005_bib9","doi-asserted-by":"crossref","first-page":"1744","DOI":"10.1109\/4.881222","article-title":"A parallel vector-quantization processor eliminating redundant calculations for real-time motion picture compression","author":"Nozawa","year":"2000","journal-title":"IEEE Journal of Solid"},{"issue":"7","key":"10.1016\/j.neucom.2010.03.005_bib10","doi-asserted-by":"crossref","first-page":"341","DOI":"10.1016\/S0141-9331(03)00062-0","article-title":"On the suitability of simd extensions for neural network simulation","volume":"27","author":"Strey","year":"2003","journal-title":"Microprocessors and Microsystems"},{"key":"10.1016\/j.neucom.2010.03.005_bib11","doi-asserted-by":"crossref","first-page":"1185","DOI":"10.1016\/S0165-1684(00)00030-X","article-title":"Applications of neural networks to digital communications\u2014a survey","volume":"80","author":"Ibnkahla","year":"2000","journal-title":"Signal Processing"},{"issue":"3","key":"10.1016\/j.neucom.2010.03.005_bib12","doi-asserted-by":"crossref","first-page":"375","DOI":"10.1109\/72.129410","article-title":"The tinmann vlsi chip","volume":"3","author":"Melton","year":"1992","journal-title":"IEEE Transactions on Neural Networks"},{"issue":"5","key":"10.1016\/j.neucom.2010.03.005_bib13","doi-asserted-by":"crossref","first-page":"447","DOI":"10.1016\/0141-9331(96)82010-2","article-title":"Tutnc: a general purpose parallel computer for neural network computations","volume":"19","author":"Hamalainen","year":"1995","journal-title":"Microprocessors and Microsystems"},{"key":"10.1016\/j.neucom.2010.03.005_bib14","doi-asserted-by":"crossref","first-page":"23","DOI":"10.1016\/S0141-9331(99)00075-7","article-title":"Parneu: general-purpose partial tree computer","volume":"24","author":"Kolinummi","year":"2000","journal-title":"Microprocessors and Microsystems"},{"issue":"5\u20136","key":"10.1016\/j.neucom.2010.03.005_bib15","doi-asserted-by":"crossref","first-page":"514","DOI":"10.1016\/j.neunet.2005.06.012","article-title":"Fpga implementation of self organizing map with digital phase locked loops","volume":"18","author":"Hikawa","year":"2005","journal-title":"Neural Networks"},{"issue":"1","key":"10.1016\/j.neucom.2010.03.005_bib16","doi-asserted-by":"crossref","first-page":"33","DOI":"10.1016\/j.micpro.2007.06.004","article-title":"A hardware design of a massive-parallel modular nn-based vector quantizer for real-time video coding","volume":"32","author":"Ramirez-Agundis","year":"2008","journal-title":"Microprocessors and Microsystems"},{"key":"10.1016\/j.neucom.2010.03.005_bib17","doi-asserted-by":"crossref","unstructured":"A. Ramirez-Agundis, R. Colom-Palero, R. Gadea-Girones, R. Diaz-Carmona, A mixed hw-sw system for fast codebook generation with the lbg algorithm, in: International Conference on Advances in Electronics and Micro-electronics, IEEE, 2008, pp. 32\u201335.","DOI":"10.1109\/ENICS.2008.31"},{"key":"10.1016\/j.neucom.2010.03.005_bib18","doi-asserted-by":"crossref","unstructured":"H. Hikawa, T. Miyanishi, K. Tamaya, Performance comparison of som based hbrid hardware classifiers, in: Proceedings of the International Joint Conference on Neural Networks, IEEE, vol. 40, 2007, pp. 1091\u20131096.","DOI":"10.1109\/IJCNN.2007.4371110"},{"issue":"4","key":"10.1016\/j.neucom.2010.03.005_bib19","doi-asserted-by":"crossref","first-page":"473","DOI":"10.1109\/4.126534","article-title":"Low-power cmos digital design","volume":"27","author":"Chandrakasan","year":"1992","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"10.1016\/j.neucom.2010.03.005_bib20","series-title":"Low-power CMOS VLSI Circuit Design","author":"Roy","year":"2000"},{"issue":"5","key":"10.1016\/j.neucom.2010.03.005_bib21","doi-asserted-by":"crossref","first-page":"448","DOI":"10.1049\/el:20030322","article-title":"Low power digital neuron for som implementations","volume":"39","author":"Cambio","year":"2003","journal-title":"Electronics Letters"},{"issue":"1","key":"10.1016\/j.neucom.2010.03.005_bib22","first-page":"49","article-title":"Bus-invert coding for low power i\/o","volume":"3","author":"Stan","year":"1995","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"10.1016\/j.neucom.2010.03.005_bib23","doi-asserted-by":"crossref","first-page":"389","DOI":"10.1016\/j.neucom.2004.05.002","article-title":"Comparator trees for winner-take-all circuits","volume":"62","author":"Hendry","year":"2004","journal-title":"Elsevier Neurocomputing"},{"key":"10.1016\/j.neucom.2010.03.005_bib24","unstructured":"PKS User Guide, Cadence Design Systems Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA, 2003."},{"key":"10.1016\/j.neucom.2010.03.005_bib25","unstructured":"\u3008www.europractice.com\u3009, supported by IST (Information Society Technologies) European Commission."},{"key":"10.1016\/j.neucom.2010.03.005_bib26","unstructured":"Cadence Design Systems,\u3008www.cadence.com\u3009, Transaction Based Verification: TestBuilder User Guide."}],"container-title":["Neurocomputing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0925231210001608?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0925231210001608?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,5,27]],"date-time":"2019-05-27T20:27:40Z","timestamp":1558988860000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0925231210001608"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12]]},"references-count":26,"journal-issue":{"issue":"1-3","published-print":{"date-parts":[[2010,12]]}},"alternative-id":["S0925231210001608"],"URL":"https:\/\/doi.org\/10.1016\/j.neucom.2010.03.005","relation":{},"ISSN":["0925-2312"],"issn-type":[{"value":"0925-2312","type":"print"}],"subject":[],"published":{"date-parts":[[2010,12]]}}}