乐胖代购免代理版

{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,2]],"date-time":"2022-04-02T15:20:28Z","timestamp":1648912828005},"reference-count":15,"publisher":"Elsevier BV","issue":"9-10","license":[{"start":{"date-parts":[[2014,9,1]],"date-time":"2014-09-01T00:00:00Z","timestamp":1409529600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"funder":[{"name":"Incheon National University Research"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Microelectronics Reliability"],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1016\/j.microrel.2014.07.044","type":"journal-article","created":{"date-parts":[[2014,8,11]],"date-time":"2014-08-11T12:01:00Z","timestamp":1407758460000},"page":"2325-2328","update-policy":"http:\/\/dx.doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":1,"title":["Hot carrier and PBTI induced degradation in silicon nanowire gate-all-around SONOS MOSFETs"],"prefix":"10.1016","volume":"54","author":[{"given":"Jin Hyung","family":"Choi","sequence":"first","affiliation":[]},{"given":"Jin-Woo","family":"Han","sequence":"additional","affiliation":[]},{"given":"Chong Gun","family":"Yu","sequence":"additional","affiliation":[]},{"given":"Jong Tae","family":"Park","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"issue":"11","key":"10.1016\/j.microrel.2014.07.044_b0005","doi-asserted-by":"crossref","first-page":"3639","DOI":"10.1109\/TED.2013.2281296","article-title":"Effects of fin width on device performance and reliability of double-gate n-type FinFETs","volume":"60","author":"Lin","year":"2013","journal-title":"IEEE Trans Electron Dev"},{"issue":"9","key":"10.1016\/j.microrel.2014.07.044_b0010","doi-asserted-by":"crossref","first-page":"1120","DOI":"10.1109\/TED.2006.872098","article-title":"Theory of interface-trap induced NBTI degradation for reduced cross section MOSFETs","volume":"53","author":"K\u00fcfl\u00fcoglu","year":"2006","journal-title":"IEEE Trans Electron Dev"},{"issue":"7","key":"10.1016\/j.microrel.2014.07.044_b0015","doi-asserted-by":"crossref","first-page":"1532","DOI":"10.1109\/16.772507","article-title":"Channel width dependence of hot-carrier induced degradation in shallow trench isolation PMOSFET\u2019s","volume":"46","author":"Ishimaru KChen","year":"1999","journal-title":"IEEE Trans Electron Dev"},{"issue":"1","key":"10.1016\/j.microrel.2014.07.044_b0020","doi-asserted-by":"crossref","first-page":"55","DOI":"10.1109\/55.974811","article-title":"Reduced floating body effects in narrow channel SOI MOSFETs","volume":"23","author":"Pretet","year":"2002","journal-title":"IEEE Electron Dev Lett"},{"key":"10.1016\/j.microrel.2014.07.044_b0025","doi-asserted-by":"crossref","first-page":"1963","DOI":"10.1016\/j.mee.2009.12.013","article-title":"Implications of fin width scaling on variability and reliability of high-K metal gate FinFETs","volume":"87","author":"Chabukswar","year":"2010","journal-title":"Microelectron Eng"},{"key":"10.1016\/j.microrel.2014.07.044_b0030","article-title":"Investigation on hot carrier reliability of gate-all-around twin Si nanowire field effect transistor","volume":"400","author":"Yeoh","year":"2009","journal-title":"Proc of IRPS"},{"issue":"5","key":"10.1016\/j.microrel.2014.07.044_b0035","doi-asserted-by":"crossref","first-page":"520","DOI":"10.1109\/LED.2009.2014975","article-title":"Vertically stacked silicon nanowire transistors fabricated by inductive plasma etching and stress-limited oxidation","volume":"30","author":"Ng","year":"2009","journal-title":"IEEE Electron Dev Lett"},{"issue":"4","key":"10.1016\/j.microrel.2014.07.044_b0040","doi-asserted-by":"crossref","first-page":"452","DOI":"10.1109\/LED.2011.2106758","article-title":"Silicon nanowire all-around gate MOSFETs built on a bulk substrate by all plasma-etching routes","volume":"32","author":"Moon","year":"2011","journal-title":"IEEE Electron Dev Lett"},{"issue":"2","key":"10.1016\/j.microrel.2014.07.044_b0045","doi-asserted-by":"crossref","first-page":"177","DOI":"10.1109\/TDMR.2005.851211","article-title":"Hot carrier degradation of HfSiON gate dielectrics with TiN electrode","volume":"5","author":"Sim","year":"2005","journal-title":"IEEE Trans Dev Mater Reliab"},{"issue":"3","key":"10.1016\/j.microrel.2014.07.044_b0050","doi-asserted-by":"crossref","first-page":"454","DOI":"10.1109\/TDMR.2009.2025178","article-title":"Competing degradation mechanisms in short-channel transistors under channel hot-carrier stress at elevated temperatures","volume":"9","author":"Amat","year":"2009","journal-title":"IEEE Trans Dev Mater Reliab"},{"key":"10.1016\/j.microrel.2014.07.044_b0055","doi-asserted-by":"crossref","unstructured":"Ramey S, Ashutosh A, Auth C, Clifford J, Hattendorf M, Hicks J, et al. Intrinsic transistor reliability improvements from 22nm tri-gate technology. In: Proc. of IRPS; 2013, 4C5.1.","DOI":"10.1109\/IRPS.2013.6532017"},{"key":"10.1016\/j.microrel.2014.07.044_b0060","unstructured":"Aminzadeh P, Alavi M, Scharfetter D. Temperature dependence of substrate current and hot carrier-induced degradation at low drain bias. In: IEEE symp VLSI technology; 1998, p. 178."},{"key":"10.1016\/j.microrel.2014.07.044_b0065","doi-asserted-by":"crossref","first-page":"268","DOI":"10.1016\/j.sse.2007.01.004","article-title":"Some issues of hot-carrier degradation and negative bias temperature instability of advanced SOI CMOS transistors","volume":"51","author":"Ioannou","year":"2007","journal-title":"Solid-State Electron"},{"issue":"4","key":"10.1016\/j.microrel.2014.07.044_b0070","doi-asserted-by":"crossref","first-page":"389","DOI":"10.1049\/el:20080392","article-title":"PBTI-associated high temperature hot-carrier degradation of nMOSFETs with metal-gate\/high-K dielectrics","volume":"29","author":"Lee","year":"2008","journal-title":"IEEE Electron Dev Lett"},{"issue":"1","key":"10.1016\/j.microrel.2014.07.044_b0075","doi-asserted-by":"crossref","first-page":"116","DOI":"10.1109\/16.658821","article-title":"Positive bias temperature instability in MOSFET\u2019s","volume":"45","author":"Zhang","year":"1998","journal-title":"IEEE Trans Electron Dev"}],"container-title":["Microelectronics Reliability"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0026271414002406?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0026271414002406?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T01:52:46Z","timestamp":1538358766000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0026271414002406"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":15,"journal-issue":{"issue":"9-10","published-print":{"date-parts":[[2014,9]]}},"alternative-id":["S0026271414002406"],"URL":"https:\/\/doi.org\/10.1016\/j.microrel.2014.07.044","relation":{},"ISSN":["0026-2714"],"issn-type":[{"value":"0026-2714","type":"print"}],"subject":[],"published":{"date-parts":[[2014,9]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"Hot carrier and PBTI induced degradation in silicon nanowire gate-all-around SONOS MOSFETs","name":"articletitle","label":"Article Title"},{"value":"Microelectronics Reliability","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.microrel.2014.07.044","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 2014 Elsevier Ltd. All rights reserved.","name":"copyright","label":"Copyright"}]}}