乐胖代购免代理版

{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,28]],"date-time":"2024-07-28T04:37:36Z","timestamp":1722141456124},"reference-count":17,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2021,7,1]],"date-time":"2021-07-01T00:00:00Z","timestamp":1625097600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2021,7,1]],"date-time":"2021-07-01T00:00:00Z","timestamp":1625097600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-017"},{"start":{"date-parts":[[2021,7,1]],"date-time":"2021-07-01T00:00:00Z","timestamp":1625097600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"},{"start":{"date-parts":[[2021,7,1]],"date-time":"2021-07-01T00:00:00Z","timestamp":1625097600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-012"},{"start":{"date-parts":[[2021,7,1]],"date-time":"2021-07-01T00:00:00Z","timestamp":1625097600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,7,1]],"date-time":"2021-07-01T00:00:00Z","timestamp":1625097600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-004"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Microprocessors and Microsystems"],"published-print":{"date-parts":[[2021,7]]},"DOI":"10.1016\/j.micpro.2021.104029","type":"journal-article","created":{"date-parts":[[2021,1,23]],"date-time":"2021-01-23T02:14:31Z","timestamp":1611368071000},"page":"104029","update-policy":"http:\/\/dx.doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":3,"special_numbering":"C","title":["A directional and scalable streaming deblocking filter hardware architecture for HEVC decoder"],"prefix":"10.1016","volume":"84","author":[{"given":"Swamy","family":"Baldev","sequence":"first","affiliation":[]},{"given":"Pradeep Kumar","family":"Rathore","sequence":"additional","affiliation":[]},{"ORCID":"http:\/\/orcid.org\/0000-0003-2645-7634","authenticated-orcid":false,"given":"Rangababu","family":"Peesapati","sequence":"additional","affiliation":[]},{"given":"Kiran Kumar","family":"Anumandla","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"issue":"12","key":"10.1016\/j.micpro.2021.104029_b1","doi-asserted-by":"crossref","first-page":"1685","DOI":"10.1109\/TCSVT.2012.2221255","article-title":"HEVC complexity and implementation analysis","volume":"22","author":"Bossen","year":"2012","journal-title":"IEEE Trans. Circuits Syst. Video Technol."},{"key":"10.1016\/j.micpro.2021.104029_b2","series-title":"ITU-T, ISO\/IEC, High Efficiency Video Coding","year":"2013"},{"issue":"3","key":"10.1016\/j.micpro.2021.104029_b3","doi-asserted-by":"crossref","first-page":"714","DOI":"10.1109\/TCE.2013.6626260","article-title":"A high performance deblocking filter hardware for high efficiency video coding","volume":"59","author":"Ozcan","year":"2013","journal-title":"IEEE Trans. Consum. Electron."},{"issue":"6","key":"10.1016\/j.micpro.2021.104029_b4","doi-asserted-by":"crossref","first-page":"1034","DOI":"10.1109\/TMM.2016.2537217","article-title":"A high-throughput and multi-parallel VLSI architecture for HEVC deblocking filter","volume":"18","author":"Zhou","year":"2016","journal-title":"IEEE Trans. Multimedia"},{"issue":"5","key":"10.1016\/j.micpro.2021.104029_b5","doi-asserted-by":"crossref","first-page":"1091","DOI":"10.1109\/TCSVT.2016.2515306","article-title":"The VLSI architecture of a highly efficient deblocking filter for HEVC systems","volume":"27","author":"Hsu","year":"2017","journal-title":"IEEE Trans. Circuits Syst. Video Technol."},{"issue":"5","key":"10.1016\/j.micpro.2021.104029_b6","doi-asserted-by":"crossref","first-page":"377","DOI":"10.1049\/iet-cds.2014.0310","article-title":"High-speed low-power very-large-scale integration architecture for dual-standard deblocking filter","volume":"9","author":"Srinivasarao","year":"2015","journal-title":"IET Circuits Dev. Syst."},{"key":"10.1016\/j.micpro.2021.104029_b7","doi-asserted-by":"crossref","unstructured":"C.M. Diniz, M. Shafique, F.V. Dalcin, S. Bampi, J. Henkel, A deblocking filter hardware architecture for the high efficiency video coding standard, in: Proc. Design Autom. Test Europe Conf. Exhibit. (DATE), Grenoble, France, 2015, pp. 1509\u20131514.","DOI":"10.7873\/DATE.2015.0856"},{"key":"10.1016\/j.micpro.2021.104029_b8","unstructured":"W. Shen, Q. Shang, S. Shen, Y. Fan, X. Zeng, A high-throughput VLSI architecture for deblocking filter in HEVC, in: Proc. IEEE Int. Symp. Circuits and Syst. (ISCAS), Beijing, China, 2013, pp. 673\u2013676."},{"key":"10.1016\/j.micpro.2021.104029_b9","doi-asserted-by":"crossref","unstructured":"W. Cheng, Y. Fan, Y. Lu, Y. Jin, X. Zeng, A high-throughput HEVC deblocking filter VLSI architecture for 8K\u00d74K application, in: Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Lisbon, Portugal, 2015, pp. 605\u2013608.","DOI":"10.1109\/ISCAS.2015.7168706"},{"key":"10.1016\/j.micpro.2021.104029_b10","doi-asserted-by":"crossref","unstructured":"L.A. Ayadi, W. Boubakri, H. Loukil, N. Masmoudi, A hardware-efficient parallel architecture for hevc deblocking filter, in: 2019 16th International Multi-Conference on Systems, Signals Devices (SSD), 2019, pp. 669\u2013673.","DOI":"10.1109\/SSD.2019.8893164"},{"key":"10.1016\/j.micpro.2021.104029_b11","doi-asserted-by":"crossref","DOI":"10.1587\/elex.16.20190500","article-title":"Five-stage pipelined dual-edge deblocking filter architecture for h. 265 video codec","author":"Christopher","year":"2019","journal-title":"IEICE Electron. Express"},{"issue":"3","key":"10.1016\/j.micpro.2021.104029_b12","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/TCE.2017.014949","article-title":"Design of streaming deblocking filter for HEVC decoder","volume":"63","author":"Peesapati","year":"2017","journal-title":"IEEE Trans. Consum. Electron."},{"issue":"1","key":"10.1016\/j.micpro.2021.104029_b13","doi-asserted-by":"crossref","first-page":"127","DOI":"10.1109\/TCE.2018.2812518","article-title":"Design and implementation of efficient streaming deblocking and SAO filter for HEVC decoder","volume":"64","author":"Baldev","year":"2018","journal-title":"IEEE Trans. Consum. Electron."},{"issue":"1","key":"10.1016\/j.micpro.2021.104029_b14","doi-asserted-by":"crossref","first-page":"41","DOI":"10.1109\/TCE.2019.2960565","article-title":"Scalable wavefront parallel streaming deblocking filter hardware for hevc decoder","volume":"66","author":"Baldev","year":"2020","journal-title":"IEEE Trans. Consum. Electron."},{"issue":"12","key":"10.1016\/j.micpro.2021.104029_b15","doi-asserted-by":"crossref","first-page":"1649","DOI":"10.1109\/TCSVT.2012.2221191","article-title":"Overview of the high efficiency video coding HEVC standard","volume":"22","author":"Sullivan","year":"2012","journal-title":"IEEE Trans. Circuits Syst. Video Technol."},{"issue":"12","key":"10.1016\/j.micpro.2021.104029_b16","doi-asserted-by":"crossref","first-page":"1755","DOI":"10.1109\/TCSVT.2012.2221529","article-title":"Sample adaptive offset in the HEVC standard","volume":"22","author":"Fu","year":"2012","journal-title":"IEEE Trans. Circuits Syst. Video Technol."},{"issue":"6","key":"10.1016\/j.micpro.2021.104029_b17","doi-asserted-by":"crossref","first-page":"1022","DOI":"10.1109\/TMM.2016.2532606","article-title":"A combined deblocking filter and SAO hardware architecture for HEVC","volume":"18","author":"Shen","year":"2016","journal-title":"IEEE Trans. Multimedia"}],"container-title":["Microprocessors and Microsystems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0141933121002015?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0141933121002015?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2023,1,4]],"date-time":"2023-01-04T22:32:12Z","timestamp":1672871532000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0141933121002015"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,7]]},"references-count":17,"alternative-id":["S0141933121002015"],"URL":"https:\/\/doi.org\/10.1016\/j.micpro.2021.104029","relation":{},"ISSN":["0141-9331"],"issn-type":[{"value":"0141-9331","type":"print"}],"subject":[],"published":{"date-parts":[[2021,7]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"A directional and scalable streaming deblocking filter hardware architecture for HEVC decoder","name":"articletitle","label":"Article Title"},{"value":"Microprocessors and Microsystems","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.micpro.2021.104029","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2021 Elsevier B.V. All rights reserved.","name":"copyright","label":"Copyright"}],"article-number":"104029"}}