{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T05:02:47Z","timestamp":1740114167095,"version":"3.37.3"},"reference-count":69,"publisher":"Elsevier BV","issue":"8","license":[{"start":{"date-parts":[[2015,11,1]],"date-time":"2015-11-01T00:00:00Z","timestamp":1446336000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Microprocessors and Microsystems"],"published-print":{"date-parts":[[2015,11]]},"DOI":"10.1016\/j.micpro.2015.06.003","type":"journal-article","created":{"date-parts":[[2015,6,20]],"date-time":"2015-06-20T00:05:06Z","timestamp":1434758706000},"page":"1204-1214","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":13,"title":["Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview"],"prefix":"10.1016","volume":"39","author":[{"given":"A.","family":"Vallero","sequence":"first","affiliation":[]},{"given":"S.","family":"Tselonis","sequence":"additional","affiliation":[]},{"given":"N.","family":"Foutris","sequence":"additional","affiliation":[]},{"given":"M.","family":"Kaliorakis","sequence":"additional","affiliation":[]},{"given":"M.","family":"Kooli","sequence":"additional","affiliation":[]},{"given":"A.","family":"Savino","sequence":"additional","affiliation":[]},{"given":"G.","family":"Politano","sequence":"additional","affiliation":[]},{"given":"A.","family":"Bosio","sequence":"additional","affiliation":[]},{"given":"G.","family":"Di Natale","sequence":"additional","affiliation":[]},{"given":"D.","family":"Gizopoulos","sequence":"additional","affiliation":[]},{"given":"S.","family":"Di Carlo","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/j.micpro.2015.06.003_b0005","doi-asserted-by":"crossref","unstructured":"S.R. Nassif, N. Mehta, Y. Cao, A resilience roadmap, in: Proceedings of the Conference on Design, Automation and Test in Europe, European Design and Automation Association, 2010, pp. 1011\u20131016.","DOI":"10.1109\/DATE.2010.5456958"},{"key":"10.1016\/j.micpro.2015.06.003_b0010","doi-asserted-by":"crossref","unstructured":"S. Krishnamohan, N.R. Mahapatra, Analysis and design of soft-error hardened latches, in: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 328\u2013331.","DOI":"10.1145\/1057661.1057740"},{"key":"10.1016\/j.micpro.2015.06.003_b0015","unstructured":"M. Hosseinabady, P. Lotfi-Kamran, G. Di Natale, S. Di Carlo, A. Benso, P. Prinetto, Single-event upset analysis and protection in high speed circuits, in: Eleventh IEEE European Test Symposium, 2006, ETS \u201906., IEEE, 2006, pp. 29\u201334."},{"key":"10.1016\/j.micpro.2015.06.003_b0020","doi-asserted-by":"crossref","unstructured":"R. Rodr\u00edguez-Monta\u00f1\u00e9s, D. Arum\u00ed, S. Manich, J. Figueras, S. Di Carlo, P. Prinetto, A. Scionti, Defective behaviour of an 8t sram cell with open defects, in: 2010 Second International Conference on Advances in System Testing and Validation Lifecycle (VALID), 2010, pp. 81\u201386, http:\/\/dx.doi.org\/10.1109\/VALID.2010.19.","DOI":"10.1109\/VALID.2010.19"},{"key":"10.1016\/j.micpro.2015.06.003_b0025","doi-asserted-by":"crossref","unstructured":"E. Taylor, Overview of new and emerging radiation resistant materials for space environment applications, in: Aerospace Conference, 2011 IEEE, 2011, pp. 1\u201311, http:\/\/dx.doi.org\/10.1109\/AERO.2011.5747389.","DOI":"10.1109\/AERO.2011.5747389"},{"key":"10.1016\/j.micpro.2015.06.003_b0030","doi-asserted-by":"crossref","unstructured":"H. Villacorta, V. Champac, S. Bota, J. Segura, Finfet sram hardening through design and technology parameters considering process variations, in: 2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2013, pp. 1\u20137, http:\/\/dx.doi.org\/10.1109\/RADECS.2013.6937372.","DOI":"10.1109\/RADECS.2013.6937372"},{"issue":"6","key":"10.1016\/j.micpro.2015.06.003_b0035","doi-asserted-by":"crossref","first-page":"4394","DOI":"10.1109\/TNS.2013.2286272","article-title":"Scalability of capacitive hardening for flip-flops in advanced technology nodes","volume":"60","author":"Diggins","year":"2013","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"10.1016\/j.micpro.2015.06.003_b0040","doi-asserted-by":"crossref","unstructured":"M. McLain, D. Hughart, D. Hanson, M. Marinella, Effects of ionizing radiation on taox-based memristive devices, in: Aerospace Conference, 2014 IEEE, 2014, pp. 1\u20139, http:\/\/dx.doi.org\/10.1109\/AERO.2014.6836501.","DOI":"10.1109\/AERO.2014.6836501"},{"key":"10.1016\/j.micpro.2015.06.003_b0045","doi-asserted-by":"crossref","unstructured":"H. Ando, Y. Yoshida, A. Inoue, I. Sugiyama, T. Asakawa, K. Morita, T. Muta, T. Motokurumada, S. Okada, H. Yamashita, Y. Satsukawa, A. Konmoto, R. Yamashita, H. Sugiyama, A 1.3GHz fifth generation sparc64 microprocessor, in: Proceedings of the 40th annual Design Automation Conference, 2003, pp. 702\u2013705.","DOI":"10.1145\/775832.776010"},{"key":"10.1016\/j.micpro.2015.06.003_b0050","doi-asserted-by":"crossref","unstructured":"C. Zambelli, M. Indaco, M. Fabiano, S. Di Carlo, P. Prinetto, P. Olivo, D. Bertozzi, A cross-layer approach for new reliability-performance trade-offs in mlc nand flash memories, in: Design, Automation Test in Europe Conference Exhibition (DATE), 2012, 2012, pp. 881\u2013886, http:\/\/dx.doi.org\/10.1109\/DATE.2012.6176622.","DOI":"10.1109\/DATE.2012.6176622"},{"issue":"6","key":"10.1016\/j.micpro.2015.06.003_b0055","doi-asserted-by":"crossref","first-page":"66","DOI":"10.1109\/MM.2013.125","article-title":"Novel mixed codes for multiple-cell upsets mitigation in static rams","volume":"33","author":"Guo","year":"2013","journal-title":"IEEE Micro"},{"issue":"4\u20135","key":"10.1016\/j.micpro.2015.06.003_b0060","doi-asserted-by":"crossref","first-page":"407","DOI":"10.1016\/j.micpro.2013.03.002","article-title":"Design and optimization of adaptable BCH codecs for NAND flash memories","volume":"37","author":"Fabiano","year":"2013","journal-title":"Microprocess. Microsyst."},{"issue":"10","key":"10.1016\/j.micpro.2015.06.003_b0065","first-page":"2211","article-title":"Analyzing the efficiency of l1 caches for reliable hybrid-voltage operation using edc codes, Very Large Scale Integration (VLSI) Systems","volume":"22","author":"Maric","year":"2014","journal-title":"IEEE Trans."},{"issue":"1","key":"10.1016\/j.micpro.2015.06.003_b0070","first-page":"127","article-title":"Enhanced memory reliability against multiple cell upsets using decimal matrix code, Very Large Scale Integration (VLSI) systems","volume":"22","author":"Guo","year":"2014","journal-title":"IEEE Trans."},{"issue":"8","key":"10.1016\/j.micpro.2015.06.003_b0075","doi-asserted-by":"crossref","first-page":"1584","DOI":"10.1109\/TC.2013.59","article-title":"Panda: a reconfigurable architecture that adapts to physical substrate variations","volume":"62","author":"Walker","year":"2013","journal-title":"IEEE Trans. Comput."},{"issue":"3","key":"10.1016\/j.micpro.2015.06.003_b0080","doi-asserted-by":"crossref","first-page":"734","DOI":"10.1109\/TC.2012.278","article-title":"High-performance and fault-tolerant 3d noc-bus hybrid architecture using arb-net-based adaptive monitoring platform","volume":"63","author":"Rahmani","year":"2014","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/j.micpro.2015.06.003_b0085","unstructured":"A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, A watchdog processor to detect data and control flow errors, in: 9th IEEE On-Line Testing Symposium, 2003, IOLTS 2003, IEEE, 2003, pp. 144\u2013148."},{"key":"10.1016\/j.micpro.2015.06.003_b0090","doi-asserted-by":"crossref","unstructured":"S.D. Carlo, G.D. Natale, R. Mariani, On-line instruction-checking in pipelined microprocessors, in: 17th Asian Test Symposium, 2008, ATS \u201908, 2008, pp. 377\u2013382, http:\/\/dx.doi.org\/10.1109\/ATS.2008.47.","DOI":"10.1109\/ATS.2008.47"},{"key":"10.1016\/j.micpro.2015.06.003_b0095","doi-asserted-by":"crossref","unstructured":"S. Di Carlo, G. Gambardella, P. Prinetto, D. Rolfo, P. Trotta, A. Vallero, A novel methodology to increase fault tolerance in autonomous fpga-based systems, in: 2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 2014, pp. 87\u201392, http:\/\/dx.doi.org\/10.1109\/IOLTS.2014.6873677.","DOI":"10.1109\/IOLTS.2014.6873677"},{"key":"10.1016\/j.micpro.2015.06.003_b0100","unstructured":"Y. Huang, C. Kintala, Software implemented fault tolerance technologies and experience, in: Proceedings of the 23rd International Symposium on Fault-Tolerant Computing, 1993, pp. 2\u20139, (cited By 33). ."},{"key":"10.1016\/j.micpro.2015.06.003_b0105","unstructured":"A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, L. Tagliaferri, Control-flow checking via regular expressions, in: Proceedings 10th Asian Test Symposium, 2001, IEEE, 2001, pp. 299\u2013303."},{"key":"10.1016\/j.micpro.2015.06.003_b0110","doi-asserted-by":"crossref","unstructured":"A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, L. Taghaferri, Data criticality estimation in software applications, in: Test Conference, 2003, Proceedings, ITC 2003, International, vol. 1, 2003, pp. 802\u2013810, http:\/\/dx.doi.org\/10.1109\/TEST.2003.1270912.","DOI":"10.1109\/TEST.2003.1270912"},{"key":"10.1016\/j.micpro.2015.06.003_b0115","unstructured":"A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, L. Tagliaferri, C. Tibaldi, Promon: a profile monitor of software applications, in: 8th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems 2005, DDECS 2005, IEEE, 2005, pp. 81\u201386."},{"key":"10.1016\/j.micpro.2015.06.003_b0120","unstructured":"A. Piotrowski, D. Makowski, G. Jab\u0142o\u0144ski, S. Tarnowski, A. Napieralski, Hardware fault tolerance implemented in software at the compiler level with special emphasis on array-variable protection, in: Proceedings of The 15th International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2008, 2008, pp. 115\u2013119, (cited By 0). ."},{"key":"10.1016\/j.micpro.2015.06.003_b0125","unstructured":"A. Piotrowski, D. Makowski, G. Jab\u00f3nski, A. Napieralski, The automatic implementation of software implemented hardware fault tolerance algorithms as a radiation-induced soft errors mitigation technique, in: IEEE Nuclear Science Symposium Conference Record, 2008, pp. 841\u2013846, (cited By 2). ."},{"year":"2006","series-title":"Software-Implemented Hardware Fault Tolerance","author":"Goloubeva","key":"10.1016\/j.micpro.2015.06.003_b0130"},{"key":"10.1016\/j.micpro.2015.06.003_b0135","unstructured":"A. DeHon, N. Carter, H. Quinn, Final Report for ccc Cross-Layer Reliability Visioning Study, March 2011. ."},{"key":"10.1016\/j.micpro.2015.06.003_b0140","unstructured":"CLERECO Consortium, Cross-Layer Early Reliability Evaluation for the Computing Continuum Official Website, 2013. ."},{"key":"10.1016\/j.micpro.2015.06.003_b0145","doi-asserted-by":"crossref","unstructured":"S. Di Carlo, A. Vallero, D. Gizopoulos, G. Di Natale, A. Grasset, R. Mariani, F. Reichenbach, Cross-layer early reliability evaluation for the computing continuum, in: 2014 17th Euromicro Conference on Digital System Design (DSD), 2014, pp. 199\u2013205. <10.1109\/DSD.2014.65>.","DOI":"10.1109\/DSD.2014.65"},{"key":"10.1016\/j.micpro.2015.06.003_b0150","doi-asserted-by":"crossref","unstructured":"S. Di Carlo, A. Vallero, D. Gizopoulos, G. Di Natale, A. Gonzalez, R. Canal, R. Mariani, M. Pipponzi, A. Grasset, P. Bonnot, F. Reichenbach, G. Rafiq, T. Loekstad, Cross-layer early reliability evaluation: challenges and promises, in: On-Line Testing Symposium (IOLTS), 2014 IEEE 20th International, 2014, pp. 228\u2013233, http:\/\/dx.doi.org\/10.1109\/IOLTS.2014.6873704.","DOI":"10.1109\/IOLTS.2014.6873704"},{"key":"10.1016\/j.micpro.2015.06.003_b0155","unstructured":"D. Buchholz, J. Dunlop, The Future of Enterprise Computing: Prepare for Compute Continuum, May 2011. ."},{"key":"10.1016\/j.micpro.2015.06.003_b0160","unstructured":"Computing Community Consortium, Ccc Visioning Study on Cross-Layer Reliability, 2015. ."},{"key":"10.1016\/j.micpro.2015.06.003_b0165","doi-asserted-by":"crossref","unstructured":"A. Bramnik, A. Sherban, N. Seifert, Timing vulnerability factors of sequential elements in modern microprocessors, in: 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013, pp. 55\u201360, http:\/\/dx.doi.org\/10.1109\/IOLTS.2013.6604051.","DOI":"10.1109\/IOLTS.2013.6604051"},{"issue":"3","key":"10.1016\/j.micpro.2015.06.003_b0170","doi-asserted-by":"crossref","first-page":"516","DOI":"10.1109\/TDMR.2004.831993","article-title":"Timing vulnerability factors of sequentials","volume":"4","author":"Seifert","year":"2004","journal-title":"IEEE Trans. Dev. Mater. Reliab."},{"key":"10.1016\/j.micpro.2015.06.003_b0175","doi-asserted-by":"crossref","unstructured":"M. Ghahroodi, M. Zwolinski, R. Wong, S.-J. Wen, Timing vulnerability factors of ultra deep-sub-micron cmos, in: 2011 16th IEEE European Test Symposium (ETS), 2011, pp. 202\u2013202, http:\/\/dx.doi.org\/10.1109\/ETS.2011.40.","DOI":"10.1109\/ETS.2011.40"},{"key":"10.1016\/j.micpro.2015.06.003_b0180","unstructured":"S.S. Mukherjee, C. Weaver, J. Emer, S.K. Reinhardt, T. Austin, A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor, in: Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture, IEEE Computer Society, 2003, p. 29."},{"issue":"6","key":"10.1016\/j.micpro.2015.06.003_b0185","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/MM.2004.85","article-title":"Razor: circuit-level correction of timing errors for low-power operation","volume":"24","author":"Ernst","year":"2004","journal-title":"IEEE Micro"},{"issue":"3","key":"10.1016\/j.micpro.2015.06.003_b0190","doi-asserted-by":"crossref","first-page":"461","DOI":"10.1145\/1816038.1816023","article-title":"Using hardware vulnerability factors to enhance avf analysis","volume":"38","author":"Sridharan","year":"2010","journal-title":"SIGARCH Comput. Archit. News"},{"issue":"11","key":"10.1016\/j.micpro.2015.06.003_b0195","doi-asserted-by":"crossref","first-page":"1521","DOI":"10.1109\/TC.2011.188","article-title":"Statistical reliability estimation of microprocessor-based systems","volume":"61","author":"Savino","year":"2012","journal-title":"IEEE Trans. Comput."},{"issue":"4","key":"10.1016\/j.micpro.2015.06.003_b0200","doi-asserted-by":"crossref","first-page":"123","DOI":"10.1145\/2248487.2150990","article-title":"Relyzer: exploiting application-level fault equivalence to analyze application resiliency to transient faults","volume":"47","author":"Hari","year":"2012","journal-title":"SIGPLAN Not."},{"key":"10.1016\/j.micpro.2015.06.003_b0205","doi-asserted-by":"crossref","unstructured":"L. Rashid, K. Pattabiraman, S. Gopalakrishnan, Towards understanding the effects of intermittent hardware faults on programs, in: 2010 International Conference on Dependable Systems and Networks Workshops (DSN-W), 2010, pp. 101\u2013106, http:\/\/dx.doi.org\/10.1109\/DSNW.2010.5542613.","DOI":"10.1109\/DSNW.2010.5542613"},{"key":"10.1016\/j.micpro.2015.06.003_b0210","doi-asserted-by":"crossref","unstructured":"R. Vadlamani, J. Zhao, W. Burleson, R. Tessier, Multicore soft error rate stabilization using adaptive dual modular redundancy, in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010, IEEE, 2010, pp. 27\u201332.","DOI":"10.1109\/DATE.2010.5457242"},{"key":"10.1016\/j.micpro.2015.06.003_b0215","doi-asserted-by":"crossref","unstructured":"M.-L. Li, P. Ramachandran, U. Karpuzcu, S.K.S. Hari, S. Adve, Accurate microarchitecture-level fault modeling for studying hardware faults, in: IEEE 15th International Symposium on High Performance Computer Architecture, 2009, HPCA 2009, 2009, pp. 105\u2013116, http:\/\/dx.doi.org\/10.1109\/HPCA.2009.4798242.","DOI":"10.1109\/HPCA.2009.4798242"},{"key":"10.1016\/j.micpro.2015.06.003_b0220","doi-asserted-by":"crossref","unstructured":"V. Sridharan, D. Kaeli, Eliminating microarchitectural dependency from architectural vulnerability, in: IEEE 15th International Symposium on High Performance Computer Architecture, 2009, HPCA 2009, 2009, pp. 117\u2013128, http:\/\/dx.doi.org\/10.1109\/HPCA.2009.4798243.","DOI":"10.1109\/HPCA.2009.4798243"},{"issue":"2","key":"10.1016\/j.micpro.2015.06.003_b0225","doi-asserted-by":"crossref","first-page":"265","DOI":"10.1145\/1353535.1346315","article-title":"Understanding the propagation of hard errors to software and implications for resilient system design","volume":"42","author":"Li","year":"2008","journal-title":"SIGOPS Oper. Syst. Rev."},{"key":"10.1016\/j.micpro.2015.06.003_b0230","doi-asserted-by":"crossref","unstructured":"A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, Static analysis of seu effects on software applications, in: Test Conference, 2002, Proceedings, International, 2002, pp. 500\u2013508, http:\/\/dx.doi.org\/10.1109\/TEST.2002.1041800.","DOI":"10.1109\/TEST.2002.1041800"},{"key":"10.1016\/j.micpro.2015.06.003_b0235","series-title":"Nanoelectronic Circuit Design","first-page":"23","article-title":"Finfet circuit design","author":"Mishra","year":"2011"},{"year":"2011","series-title":"Predictive Technology Model for Robust Nanoelectronic Design","author":"Cao","key":"10.1016\/j.micpro.2015.06.003_b0240"},{"key":"10.1016\/j.micpro.2015.06.003_b0245","unstructured":"R.M. Sinnamon, J.D. Andrews, Fault tree analysis and binary decision diagrams, in: Reliability and Maintainability Symposium, 1996 Proceedings, International Symposium on Product Quality and Integrity, Annual, IEEE, 1996, pp. 215\u2013222."},{"key":"10.1016\/j.micpro.2015.06.003_b0250","doi-asserted-by":"crossref","unstructured":"S. Distefano, A. Puliafito, Dynamic reliability block diagrams vs dynamic fault trees, in: Reliability and Maintainability Symposium, 2007, RAMS\u201907, Annual, IEEE, 2007, pp. 71\u201376.","DOI":"10.1109\/RAMS.2007.328095"},{"key":"10.1016\/j.micpro.2015.06.003_b0255","doi-asserted-by":"crossref","unstructured":"C. Ciufudean, B. Satco, C. Filote, Reliability markov chains for security data transmitter analysis, in: The Second International Conference on Availability, Reliability and Security, 2007, ARES 2007, IEEE, 2007, pp. 886\u2013894.","DOI":"10.1109\/ARES.2007.122"},{"key":"10.1016\/j.micpro.2015.06.003_b0260","doi-asserted-by":"crossref","first-page":"2590","DOI":"10.4028\/www.scientific.net\/AMM.347-350.2590","article-title":"Bayesian networks application in multi-state system reliability analysis","volume":"347","author":"Zhai","year":"2013","journal-title":"Appl. Mech. Mater."},{"issue":"3","key":"10.1016\/j.micpro.2015.06.003_b0265","doi-asserted-by":"crossref","first-page":"197","DOI":"10.1007\/BF00994016","article-title":"Learning Bayesian networks: the combination of knowledge and statistical data","volume":"20","author":"Heckerman","year":"1995","journal-title":"Mach. Learn."},{"key":"10.1016\/j.micpro.2015.06.003_b0270","doi-asserted-by":"crossref","unstructured":"N. Foutris, M. Kaliorakis, S. Tselonis, D. Gizopoulos, Versatile architecture-level fault injection framework for reliability evaluation: a first report, in: On-Line Testing Symposium (IOLTS), 2014 IEEE 20th International, IEEE, 2014, pp. 140\u2013145.","DOI":"10.1109\/IOLTS.2014.6873686"},{"key":"10.1016\/j.micpro.2015.06.003_b0275","doi-asserted-by":"crossref","unstructured":"A. Patel, F. Afram, S. Chen, K. Ghose, Marss: a full system simulator for multicore x86 cpus, in: Proceedings of the 48th Design Automation Conference, ACM, 2011, pp. 1050\u20131055.","DOI":"10.1145\/2024724.2024954"},{"key":"10.1016\/j.micpro.2015.06.003_b0280","doi-asserted-by":"crossref","unstructured":"M.T. Yourst, Ptlsim: a cycle accurate full system x86\u201364 microarchitectural simulator, in: IEEE International Symposium on Performance Analysis of Systems & Software, 2007, ISPASS 2007, IEEE, 2007, pp. 23\u201334.","DOI":"10.1109\/ISPASS.2007.363733"},{"key":"10.1016\/j.micpro.2015.06.003_b0285","unstructured":"T. Lindholm, F. Yellin, G. Bracha, A. Buckley, The Java Virtual Machine Specification, February 2013. ."},{"key":"10.1016\/j.micpro.2015.06.003_b0290","unstructured":"Microsoft Corporation, December 2014. ."},{"key":"10.1016\/j.micpro.2015.06.003_b0295","unstructured":"Xamarin, Mono Project, December 2014. ."},{"key":"10.1016\/j.micpro.2015.06.003_b0300","unstructured":"C. Lattner, V. Adve, Llvm: a compilation framework for lifelong program analysis & transformation, in: International Symposium on Code Generation and Optimization, 2004, CGO 2004, IEEE, 2004, pp. 75\u201386."},{"volume":"vol. 17","year":"2000","author":"Bushnell","key":"10.1016\/j.micpro.2015.06.003_b0305"},{"year":"2011","series-title":"Architecture Design for Soft Errors","author":"Mukherjee","key":"10.1016\/j.micpro.2015.06.003_b0310"},{"issue":"3","key":"10.1016\/j.micpro.2015.06.003_b0315","doi-asserted-by":"crossref","first-page":"188","DOI":"10.1109\/TDSC.2006.40","article-title":"Restore: Symptom-based soft error detection in microprocessors","volume":"3","author":"Wang","year":"2006","journal-title":"IEEE Trans. Dependable Secure Comput."},{"issue":"11","key":"10.1016\/j.micpro.2015.06.003_b0320","doi-asserted-by":"crossref","first-page":"1248","DOI":"10.1109\/12.544481","article-title":"A gate-level simulation environment for alpha-particle-induced transient faults","volume":"45","author":"Cha","year":"1996","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/j.micpro.2015.06.003_b0325","unstructured":"S. Mirkhani, M. Lavasani, Z. Navabi, Hierarchical fault simulation using behavioral and gate level hardware models, in: Proceedings of the 11th Asian Test Symposium, 2002, (ATS\u201902), IEEE, 2002, pp. 374\u2013379."},{"key":"10.1016\/j.micpro.2015.06.003_b0330","unstructured":"A. Thomas, K. Pattabiraman, LLFI: an intermediate code level fault injector for soft computing applications, in: Workshop on Silicon Errors in Logic \u2013 System Effects (SELSE), 2013."},{"key":"10.1016\/j.micpro.2015.06.003_b0335","doi-asserted-by":"crossref","unstructured":"J. Wei, A. Thomas, G. Li, K. Pattabiraman, Quantifying the accuracy of high-level fault injection techniques for hardware faults, in: 2014 44th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN), 2014, pp. 375\u2013382, http:\/\/dx.doi.org\/10.1109\/DSN.2014.2.","DOI":"10.1109\/DSN.2014.2"},{"key":"10.1016\/j.micpro.2015.06.003_b0340","doi-asserted-by":"crossref","unstructured":"V. Sharma, A. Haran, Z. Rakamaric, G. Gopalakrishnan, Towards formal approaches to system resilience, in: 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing (PRDC), 2013, pp. 41\u201350, http:\/\/dx.doi.org\/10.1109\/PRDC.2013.14.","DOI":"10.1109\/PRDC.2013.14"},{"key":"10.1016\/j.micpro.2015.06.003_b0345","unstructured":"C. Lattner, The LLVM Compiler Infrastructure. ."}],"container-title":["Microprocessors and Microsystems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0141933115000824?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0141933115000824?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,10,26]],"date-time":"2019-10-26T08:16:22Z","timestamp":1572077782000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0141933115000824"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,11]]},"references-count":69,"journal-issue":{"issue":"8","published-print":{"date-parts":[[2015,11]]}},"alternative-id":["S0141933115000824"],"URL":"https:\/\/doi.org\/10.1016\/j.micpro.2015.06.003","relation":{},"ISSN":["0141-9331"],"issn-type":[{"type":"print","value":"0141-9331"}],"subject":[],"published":{"date-parts":[[2015,11]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview","name":"articletitle","label":"Article Title"},{"value":"Microprocessors and Microsystems","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.micpro.2015.06.003","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 2015 Elsevier B.V. All rights reserved.","name":"copyright","label":"Copyright"}]}}