{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T07:54:40Z","timestamp":1719906880921},"reference-count":44,"publisher":"Elsevier BV","issue":"3","content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Microprocessors and Microsystems"],"published-print":{"date-parts":[[2013,5]]},"DOI":"10.1016\/j.micpro.2013.02.003","type":"journal-article","created":{"date-parts":[[2013,2,19]],"date-time":"2013-02-19T10:28:11Z","timestamp":1361269691000},"page":"333-344","update-policy":"http:\/\/dx.doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":10,"title":["Traffic engineered NoC for streaming applications"],"prefix":"10.1016","volume":"37","author":[{"given":"Basavaraj","family":"Talwar","sequence":"first","affiliation":[]},{"given":"Bharadwaj","family":"Amrutur","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/j.micpro.2013.02.003_b0005","doi-asserted-by":"crossref","unstructured":"W. Dally, B. Towles, Route packets, not wires: on-chip interconnection networks, in: Proceedings of Design Automation Conference, 2001, pp. 684\u2013689.","DOI":"10.1145\/378239.379048"},{"key":"10.1016\/j.micpro.2013.02.003_b0010","series-title":"Networks on Chip","year":"2003"},{"key":"10.1016\/j.micpro.2013.02.003_b0015","series-title":"Networks on Chips: Technology and Tools","year":"2006"},{"key":"10.1016\/j.micpro.2013.02.003_b0020","series-title":"Solid-State Circuits Conference Digest of Technical Papers (ISSCC)","first-page":"88","article-title":"Tile64 \u2013 processor: a 64-core soc with mesh interconnect","author":"Bell","year":"2008"},{"key":"10.1016\/j.micpro.2013.02.003_b0025","series-title":"Solid-State Circuits Conference Digest of Technical Papers (ISSCC)","first-page":"110","article-title":"A 4.1tb\/s bisection-bandwidth 560gb\/s\/w streaming circuit-switched 8\u00d78 mesh network-on-chip in 45nm cmos","author":"Anders","year":"2010"},{"key":"10.1016\/j.micpro.2013.02.003_b0030","unstructured":"P.T. Wolkotte, G.J.M. Smit, G.K. Rauwerda, L.T. Smit, An energy efficient reconfigurable circuit switched network-on-chip, in: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS05) \u2013 12th Reconfigurable Architecture Workshop (RAW 2005), p. 155a. ISBN: 0-7695."},{"key":"10.1016\/j.micpro.2013.02.003_b0035","series-title":"Solid-State Circuits Conference, 2008 (A-SSCC \u201908)","first-page":"189","article-title":"A 76.8gb\/s 46mw low-latency network-on-chip for real-time object recognition processor","author":"Kim","year":"2008"},{"key":"10.1016\/j.micpro.2013.02.003_b0040","doi-asserted-by":"crossref","first-page":"560","DOI":"10.1109\/TCSVT.2003.815165","article-title":"Overview of the h.264\/avc video coding standard","volume":"13","author":"Wiegand","year":"2003","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"10.1016\/j.micpro.2013.02.003_b0045","doi-asserted-by":"crossref","first-page":"603","DOI":"10.1016\/j.micpro.2011.06.009","article-title":"A study of 3d network-on-chip design for data parallel h.264 coding","volume":"35","author":"Xu","year":"2011","journal-title":"Microprocessors and Microsystems"},{"key":"10.1016\/j.micpro.2013.02.003_b0050","doi-asserted-by":"crossref","first-page":"294","DOI":"10.1049\/ip-cdt:20030830","article-title":"Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip","volume":"150","author":"Rijpkema","year":"2003","journal-title":"IEE Proceedings Computers and Digital Techniques"},{"key":"10.1016\/j.micpro.2013.02.003_b0055","doi-asserted-by":"crossref","first-page":"711","DOI":"10.1109\/TVLSI.2004.830919","article-title":"An architecture and compiler for scalable on-chip communication","volume":"12","author":"Liang","year":"2004","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"10.1016\/j.micpro.2013.02.003_b0060","doi-asserted-by":"crossref","first-page":"32","DOI":"10.1109\/MM.2004.1268991","article-title":"Asynchronous interconnect for synchronous soc design","volume":"24","author":"Lines","year":"2004","journal-title":"IEEE Micro"},{"key":"10.1016\/j.micpro.2013.02.003_b0065","series-title":"Proceedings of the 17th International Symposium on Parallel and Distributed Processing, IPDPS \u201903","article-title":"Socbus: Switched network on chip for hard real time embedded systems","author":"Wiklund","year":"2003"},{"key":"10.1016\/j.micpro.2013.02.003_b0070","unstructured":"E. Beigne, F. Clermidy, P. Vivet, A. Clouard, M. Renaudin, An asynchronous noc architecture providing low latency service and its multi-level design framework, in: Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems, 2005 (ASYNC 2005), 2005, pp. 54\u201363."},{"key":"10.1016\/j.micpro.2013.02.003_b0075","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1109\/TCAD.2008.2010691","article-title":"Outstanding research problems in noc design: system, microarchitecture, and circuit perspectives","volume":"28","author":"Marculescu","year":"2009","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"10.1016\/j.micpro.2013.02.003_b0080","doi-asserted-by":"crossref","first-page":"105","DOI":"10.1016\/j.sysarc.2003.07.004","article-title":"Qnoc: Qos architecture and design process for network on chip","volume":"50","author":"Bolotin","year":"2004","journal-title":"Journal of Systems Architecture"},{"key":"10.1016\/j.micpro.2013.02.003_b0085","doi-asserted-by":"crossref","first-page":"223","DOI":"10.1109\/JSSC.2007.909339","article-title":"A reconfigurable baseband platform based on an asynchronous network-on-chip","volume":"43","author":"Lattard","year":"2008","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"10.1016\/j.micpro.2013.02.003_b0090","doi-asserted-by":"crossref","first-page":"36","DOI":"10.1109\/MM.2002.1044298","article-title":"An interconnect architecture for networking systems on chips","volume":"22","author":"Karim","year":"2002","journal-title":"IEEE Micro"},{"key":"10.1016\/j.micpro.2013.02.003_b0095","doi-asserted-by":"crossref","first-page":"185","DOI":"10.1007\/s11265-006-7270-6","article-title":"Hibi communication network for system-on-chip","volume":"43","author":"Salminen","year":"2006","journal-title":"Journal of VLSI Signal Processing Systems"},{"key":"10.1016\/j.micpro.2013.02.003_b0100","unstructured":"X. Wu, Y. Wu, L. Wang, X. Yang, Qos router with both soft and hard guarantee for network-on-chip, in: NORCHIP, 2009, pp. 1\u20136."},{"key":"10.1016\/j.micpro.2013.02.003_b0105","doi-asserted-by":"crossref","unstructured":"Y. Salah, R. Tourki, Design and fpga implementation of a qos router for networks-on-chip, in: 3rd International Conference on Next Generation Networks and Services (NGNS), 2011, pp. 84\u201389.","DOI":"10.1109\/NGNS.2011.6142551"},{"key":"10.1016\/j.micpro.2013.02.003_b0110","series-title":"Proceedings of the 43rd annual Design Automation Conference, DAC \u201906","first-page":"143","article-title":"Evaluation and design trade-offs between circuit-switched and packet-switched nocs for application-specific socs","author":"Chang","year":"2006"},{"key":"10.1016\/j.micpro.2013.02.003_b0115","doi-asserted-by":"crossref","unstructured":"T. Richardson, C. Nicopoulos, D. Park, V. Narayanan, Y. Xie, C. Das, V. Degalahal, A hybrid soc interconnect with dynamic tdma-based transaction-less buses and on-chip networks, in: 19th International Conference on VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design, 2006, 8 pp.","DOI":"10.1109\/VLSID.2006.10"},{"key":"10.1016\/j.micpro.2013.02.003_b0120","unstructured":"J. Hu, Y. Deng, R. Marculescu, System-level point-to-point communication synthesis using floorplanning information, in: Proc. ASP-DAC, 2002, pp. 573\u2013579."},{"key":"10.1016\/j.micpro.2013.02.003_b0125","doi-asserted-by":"crossref","unstructured":"D. Castells-Rufas, J. Joven, J. Carrabina, A validation and performance evaluation tool for protonoc, in: International Symposium on System-on-Chip, 2006, pp. 1\u20134.","DOI":"10.1109\/ISSOC.2006.321991"},{"key":"10.1016\/j.micpro.2013.02.003_b0130","unstructured":"T. Bjerregaard, J. Sparso, A router architecture for connection-oriented service guarantees in the mango clockless network-on-chip, in: Proceedings of Design, Automation and Test in Europe, vol. 2, 2005, pp. 1226\u20131231."},{"key":"10.1016\/j.micpro.2013.02.003_b0135","series-title":"Proceedings of the 2010 43rd Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO \u201943","first-page":"409","article-title":"Loft: a high performance network-on-chip providing quality-of-service support","author":"Ouyang","year":"2010"},{"key":"10.1016\/j.micpro.2013.02.003_b0140","doi-asserted-by":"crossref","first-page":"414","DOI":"10.1109\/MDT.2005.99","article-title":"\u00e6thereal network on chip: concepts, architectures, and implementations","volume":"22","author":"Goossens","year":"2005","journal-title":"IEEE Design Test of Computers"},{"key":"10.1016\/j.micpro.2013.02.003_b0145","unstructured":"E. Rijpkema, K. Goossens, P. Wielage, A router architecture for networks on silicon, in: Proceedings of Progress 2001, 2nd Workshop on Embedded Systems, 2001, pp. 181\u2013188."},{"key":"10.1016\/j.micpro.2013.02.003_b0150","series-title":"Proceedings of the Design, Automation & Test in Europe Conference and Exhibition","first-page":"250","article-title":"Aelite: a flit-synchronous network on chip with composable and predictable services","author":"Hansson","year":"2009"},{"key":"10.1016\/j.micpro.2013.02.003_b0155","article-title":"daelite: a tdm noc supporting qos, multicast, and fast connection set-up","volume":"99","author":"Stefan","year":"2012","journal-title":"IEEE Transactions on Computers"},{"key":"10.1016\/j.micpro.2013.02.003_b0160","series-title":"Asynchronous Transfer Mode Switching","author":"Joel","year":"1993"},{"key":"10.1016\/j.micpro.2013.02.003_b0165","article-title":"Multiprotocol Label Switching Architecture","volume":"3031","author":"Rosen","year":"2001","journal-title":"RFC"},{"key":"10.1016\/j.micpro.2013.02.003_b0170","unstructured":"M. Kim, D. Kim, G. Sobelman, Network-on-chip quality-of-service through multiprotocol label switching, in: Proceedings of IEEE International Symposium on Circuits and Systems, 2006 (ISCAS 2006), 2006, p. 1843."},{"key":"10.1016\/j.micpro.2013.02.003_b0175","doi-asserted-by":"crossref","first-page":"1425","DOI":"10.1109\/TPDS.2006.166","article-title":"A simple data transfer technique using local address for networks-on-chips","volume":"17","author":"Koibuchi","year":"2006","journal-title":"IEEE Transactions on Parallel Distribution Systems"},{"key":"10.1016\/j.micpro.2013.02.003_b0180","unstructured":"Tilera Corporation, TILE-Gx 3000 Series Overview, 2011."},{"key":"10.1016\/j.micpro.2013.02.003_b0185","doi-asserted-by":"crossref","first-page":"97","DOI":"10.1007\/BF01585506","article-title":"Optimal flows in networks with sources and sinks","volume":"7","author":"Megiddo","year":"1974","journal-title":"Mathematical Programming"},{"key":"10.1016\/j.micpro.2013.02.003_b0190","doi-asserted-by":"crossref","first-page":"210","DOI":"10.4153\/CJM-1957-024-0","article-title":"A simple algorithm for finding maximal network flows and an application to the hitchcock problem","volume":"9","author":"Ford","year":"1957","journal-title":"Canadian Journal of Mathematics"},{"key":"10.1016\/j.micpro.2013.02.003_b0195","unstructured":"Icarus iverilog, 2011. ."},{"key":"10.1016\/j.micpro.2013.02.003_b0200","unstructured":"ITRS, International Technology Roadmap for Semiconductors, 2011."},{"key":"10.1016\/j.micpro.2013.02.003_b0205","doi-asserted-by":"crossref","unstructured":"R. Nagpal, M. Arvind, Y.N. Srikanth, B. Amrutur, Intacte: tool for interconnect modelling, in: Proc. of 2007 Intl Conf. on Compilers, Architecture and Synthesis for Embedded Systems (CASES 2007), 2007, pp. 238\u2013247.","DOI":"10.1145\/1289881.1289923"},{"key":"10.1016\/j.micpro.2013.02.003_b0210","unstructured":"TileraGX, Tile-GX Processor Family, 2011."},{"key":"10.1016\/j.micpro.2013.02.003_b0215","doi-asserted-by":"crossref","first-page":"1182","DOI":"10.1109\/TC.2008.82","article-title":"Concepts and implementation of spatial division multiplexing for guaranteed throughput in networks-on-chip","volume":"57","author":"Leroy","year":"2008","journal-title":"IEEE Transactions on Computers"},{"key":"10.1016\/j.micpro.2013.02.003_b0220","unstructured":"N.H.E. Weste, D. Harris, CMOS VLSI Design \u2013 A Circuit and Systems Perspective, Addison Wesley 2011, p. 256."}],"container-title":["Microprocessors and Microsystems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0141933113000239?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0141933113000239?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,7,9]],"date-time":"2019-07-09T18:08:01Z","timestamp":1562695681000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0141933113000239"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,5]]},"references-count":44,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2013,5]]}},"alternative-id":["S0141933113000239"],"URL":"https:\/\/doi.org\/10.1016\/j.micpro.2013.02.003","relation":{},"ISSN":["0141-9331"],"issn-type":[{"value":"0141-9331","type":"print"}],"subject":[],"published":{"date-parts":[[2013,5]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"Traffic engineered NoC for streaming applications","name":"articletitle","label":"Article Title"},{"value":"Microprocessors and Microsystems","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.micpro.2013.02.003","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 2013 Elsevier B.V. All rights reserved.","name":"copyright","label":"Copyright"}]}}