乐胖代购免代理版

{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,16]],"date-time":"2024-09-16T13:24:25Z","timestamp":1726493065727},"reference-count":30,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2017,8,1]],"date-time":"2017-08-01T00:00:00Z","timestamp":1501545600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"funder":[{"name":"Xilinx University Program"},{"DOI":"10.13039\/501100001691","name":"Japanese Society for the Promotion of Science (JSPS)","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001691","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Journal of Parallel and Distributed Computing"],"published-print":{"date-parts":[[2017,8]]},"DOI":"10.1016\/j.jpdc.2017.01.029","type":"journal-article","created":{"date-parts":[[2017,2,16]],"date-time":"2017-02-16T07:47:14Z","timestamp":1487231234000},"page":"106-120","update-policy":"http:\/\/dx.doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":9,"special_numbering":"C","title":["A low-area unified hardware architecture for the AES and the cryptographic hash function Gr\u00f8stl"],"prefix":"10.1016","volume":"106","author":[{"given":"Nuray","family":"At","sequence":"first","affiliation":[]},{"given":"Jean-Luc","family":"Beuchat","sequence":"additional","affiliation":[]},{"given":"Eiji","family":"Okamoto","sequence":"additional","affiliation":[]},{"given":"Ismail","family":"San","sequence":"additional","affiliation":[]},{"given":"Teppei","family":"Yamazaki","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/j.jpdc.2017.01.029_br000005","series-title":"Proceedings of the International Conference on Security and Cryptography\u2013SECRYPT 2011","first-page":"124","article-title":"Byte slicing Gr\u00f8stl\u2013optimized intel AES-NI and 8-bit implementations of the SHA-3 finalist Gr\u00f8stl","author":"Aoki","year":"2011"},{"issue":"2","key":"10.1016\/j.jpdc.2017.01.029_br000010","doi-asserted-by":"crossref","first-page":"485","DOI":"10.1109\/TCSI.2013.2278385","article-title":"Compact hardware implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA","volume":"61","author":"At","year":"2014","journal-title":"IEEE Trans. Circuits Syst. I"},{"key":"10.1016\/j.jpdc.2017.01.029_br000015","series-title":"Proceedings of the Fifth IFIP International Conference on New Technologies, Mobility and Security\u2013NTMS 2012","article-title":"Compact implementation of Threefish and Skein on FPGA","author":"At","year":"2012"},{"key":"10.1016\/j.jpdc.2017.01.029_br000020","unstructured":"J.-P. Aumasson, L. Henzen, W. Meier, R. Phan, SHA-3 proposal BLAKE (version 1.4), (Jan. 2011). available at http:\/\/www.131002.net\/blake."},{"key":"10.1016\/j.jpdc.2017.01.029_br000025","unstructured":"R. Benadjila, O. Billet, H. Gilbert, G. Macario-Rat, T. Peyrin, M. Robshaw, Y. Seurin, SHA-3 proposal: ECHO, 2009. available at http:\/\/crypto.rd.francetelecom.com\/echo."},{"key":"10.1016\/j.jpdc.2017.01.029_br000030","series-title":"Advances in Cryptology\u2013ASIACRYPT 2009","first-page":"162","article-title":"The intel AES instructions set and the SHA-3 candidates","volume":"vol. 5912","author":"Benadjila","year":"2009"},{"key":"10.1016\/j.jpdc.2017.01.029_br000035","unstructured":"G. Bertoni, J. Daemen, M. Peeters, G. Van Assche, R. Van Keer, Keccak implementation overview (version 3.1) (Sep. 2011)."},{"issue":"2","key":"10.1016\/j.jpdc.2017.01.029_br000040","doi-asserted-by":"crossref","first-page":"101","DOI":"10.1007\/s13389-011-0009-8","article-title":"A low-area unified hardware architecture for the AES and the cryptographic hash function ECHO","volume":"1","author":"Beuchat","year":"2011","journal-title":"J. Cryptogr. Eng."},{"key":"10.1016\/j.jpdc.2017.01.029_br000045","series-title":"Progress in Cryptology\u2013AFRICACRYPT 2008","first-page":"16","article-title":"Implementation of the AES-128 on Virtex-5 FPGAs","volume":"vol. 5023","author":"Bulens","year":"2008"},{"year":"2002","series-title":"The Design of Rijndael","author":"Daemen","key":"10.1016\/j.jpdc.2017.01.029_br000050"},{"key":"10.1016\/j.jpdc.2017.01.029_br000055","series-title":"Cryptographic Engineering","first-page":"235","article-title":"FPGA and ASIC implementations of the AES","author":"Gaj","year":"2009"},{"key":"10.1016\/j.jpdc.2017.01.029_br000060","unstructured":"P. Gauravaram, L. Knudsen, K. Matusiewicz, F. Mendel, C. Rechberger, M. Schl\u00e4ffer, S. Thomsen, Gr\u00f8stl\u2013a SHA-3 candidate, 2011. available at http:\/\/www.groestl.info."},{"key":"10.1016\/j.jpdc.2017.01.029_br000065","series-title":"Cryptographic Hardware and Embedded Systems\u2013CHES 2011","first-page":"33","article-title":"Generic side-channel countermeasures for reconfigurable devices","volume":"vol. 6917","author":"G\u00fcneysu","year":"2011"},{"key":"10.1016\/j.jpdc.2017.01.029_br000070","series-title":"Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools\u2013DSD\u201906","first-page":"577","article-title":"Design and implementation of low-area and low-power AES encryption hardware core","author":"H\u00e4m\u00e4l\u00e4inen","year":"2006"},{"key":"10.1016\/j.jpdc.2017.01.029_br000075","unstructured":"Helion Technology, FULL DATASHEET\u2013Tiny hash core family for Xilinx FPGA, revision 2.0 (11\/06\/2010)."},{"key":"10.1016\/j.jpdc.2017.01.029_br000080","unstructured":"Helion Technology, OVERVIEW DATASHEET\u2013Ultra-low resource AES (Rijndael) cores for Xilinx FPGA, revision 1.3.0."},{"key":"10.1016\/j.jpdc.2017.01.029_br000085","unstructured":"E. Homsirikamol, M. Rogawski, K. Gaj, Comparing hardware performance of round 3 SHA-3 candidates using multiple hardware architectures in Xilinx and Altera FPGAs, in: Proceedings of the ECRYPT II Hash Workshop, 2011."},{"key":"10.1016\/j.jpdc.2017.01.029_br000090","unstructured":"K. J\u00e4rvinen, Sharing resources between AES and the SHA-3 second round candidates Fugue and Gr\u00f8stl, in: The Second SHA-3 Candidate Conference, 2010."},{"key":"10.1016\/j.jpdc.2017.01.029_br000095","doi-asserted-by":"crossref","unstructured":"B. Jungk, Evaluation of compact FPGA implementations for all SHA-3 finalists, in: The Third SHA-3 Candidate Conference, 2012.","DOI":"10.1109\/ReConFig.2011.16"},{"key":"10.1016\/j.jpdc.2017.01.029_br000100","series-title":"8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip\u2013ReCoSoC 2013","first-page":"1","article-title":"Among slow dwarfs and fast giants: A systematic design space exploration of KECCAK","author":"Jungk","year":"2013"},{"key":"10.1016\/j.jpdc.2017.01.029_br000105","doi-asserted-by":"crossref","unstructured":"J.-P. Kaps, P. Yalla, K. Surapathi, B. Habib, S. Vadlamudi, S. Gurung, Lightweight implementations of SHA-3 finalists on FPGAs, in: The Third SHA-3 Candidate Conference, 2012.","DOI":"10.1007\/978-3-642-25578-6_20"},{"key":"10.1016\/j.jpdc.2017.01.029_br000110","doi-asserted-by":"crossref","unstructured":"S. Kerckhof, F. Durvaux, N. Veyrat-Charvillon, F. Regazzoni, G. Meurice de Dormale, F.-X. Standaert, Compact FPGA implementations of the five SHA-3 finalists, in: Proceedings of the ECRYPT II Hash Workshop, 2011.","DOI":"10.1007\/978-3-642-27257-8_14"},{"issue":"5","key":"10.1016\/j.jpdc.2017.01.029_br000115","doi-asserted-by":"crossref","first-page":"827","DOI":"10.1109\/TVLSI.2011.2128353","article-title":"Fair and consistent hardware evaluation of fourteen round two SHA-3 candidates","volume":"20","author":"Kne\u017eevi\u0107","year":"2012","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"10.1016\/j.jpdc.2017.01.029_br000120","doi-asserted-by":"crossref","unstructured":"K. Latif, M. Rao, A. Aziz, A. Mahboob, Efficient hardware implementations and hardware performance evaluation of SHA-3 finalists, in: The Third SHA-3 Candidate Conference, 2012.","DOI":"10.51758\/AGJSR-01-2012-0003"},{"key":"10.1016\/j.jpdc.2017.01.029_br000125","series-title":"Smart Card Research and Advanced Applications\u2013CARDIS 2012","first-page":"173","article-title":"Putting together what fits together\u2013Gr\u00c6Stl","volume":"vol. 7771","author":"Pelnar","year":"2013"},{"key":"10.1016\/j.jpdc.2017.01.029_br000130","doi-asserted-by":"crossref","unstructured":"M. Rogawski, K. Gaj, A high-speed unified hardware architecture for AES and the SHA-3 candidate Gr\u00f8stl, in: Proceedings of the 15th Euromicro Conference on Digital System Design, 2012.","DOI":"10.1109\/DSD.2012.8"},{"issue":"5","key":"10.1016\/j.jpdc.2017.01.029_br000135","first-page":"231","article-title":"Compact Keccak hardware architecture for data integrity and authentication on FPGAs","volume":"21","author":"San","year":"2012","journal-title":"Inf. Secur. J.: Global Perspect."},{"key":"10.1016\/j.jpdc.2017.01.029_br000140","series-title":"Security in Pervasive Computing","first-page":"201","article-title":"Security and privacy aspects of low-cost radio frequency identification systems","volume":"vol. 2802","author":"Weis","year":"2004"},{"year":"2012","series-title":"Compact implementation of hash functions on FPGA","author":"Yamazaki","key":"10.1016\/j.jpdc.2017.01.029_br000145"},{"key":"10.1016\/j.jpdc.2017.01.029_br000150","series-title":"Computational Science and Its Applications\u2013ICCSA 2006","first-page":"296","article-title":"Hash-based RFID security protocol using randomly key-changed identification procedure","volume":"vol. 3983","author":"Zhai","year":"2006"}],"container-title":["Journal of Parallel and Distributed Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0743731517300485?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0743731517300485?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2022,7,24]],"date-time":"2022-07-24T03:50:05Z","timestamp":1658634605000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0743731517300485"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,8]]},"references-count":30,"alternative-id":["S0743731517300485"],"URL":"https:\/\/doi.org\/10.1016\/j.jpdc.2017.01.029","relation":{},"ISSN":["0743-7315"],"issn-type":[{"type":"print","value":"0743-7315"}],"subject":[],"published":{"date-parts":[[2017,8]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"A low-area unified hardware architecture for the AES and the cryptographic hash function Gr\u00f8stl","name":"articletitle","label":"Article Title"},{"value":"Journal of Parallel and Distributed Computing","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.jpdc.2017.01.029","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2017 Elsevier Inc. All rights reserved.","name":"copyright","label":"Copyright"}]}}