乐胖代购免代理版

{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,5,30]],"date-time":"2023-05-30T15:17:09Z","timestamp":1685459829013},"reference-count":15,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2018,2,23]],"date-time":"2018-02-23T00:00:00Z","timestamp":1519344000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Wireless Pers Commun"],"published-print":{"date-parts":[[2018,11]]},"DOI":"10.1007\/s11277-018-5428-8","type":"journal-article","created":{"date-parts":[[2018,2,23]],"date-time":"2018-02-23T14:15:34Z","timestamp":1519395334000},"page":"99-115","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":6,"title":["Performance Analysis in Digital Circuits for Process Corner Variations, Slew-Rate and Load Capacitance"],"prefix":"10.1007","volume":"103","author":[{"given":"R.","family":"Udaiyakumar","sequence":"first","affiliation":[]},{"given":"Senoj","family":"Joseph","sequence":"additional","affiliation":[]},{"given":"T. V. P.","family":"Sundararajan","sequence":"additional","affiliation":[]},{"given":"D.","family":"Vigneswaran","sequence":"additional","affiliation":[]},{"given":"R.","family":"Maheswar","sequence":"additional","affiliation":[]},{"given":"Iraj S.","family":"Amiri","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2018,2,23]]},"reference":[{"key":"5428_CR1","volume-title":"Nano-CMOS circuit and physical design","author":"BP Wong","year":"2005","unstructured":"Wong, B. P., Mittal, A., Cao, Y., & Starr, G. (2005). Nano-CMOS circuit and physical design. New York: Wiley Interscience."},{"issue":"3","key":"5428_CR2","doi-asserted-by":"publisher","first-page":"93","DOI":"10.4313\/TEEM.2010.11.3.093","volume":"11","author":"Y-B Kim","year":"2010","unstructured":"Kim, Y.-B. (2010). Challenges for nanoscale MOSFETs and emerging nanoelectronics. Transactions on Electrical And Electronic Materials, 11(3), 93\u2013105.","journal-title":"Transactions on Electrical And Electronic Materials"},{"issue":"2\/3","key":"5428_CR3","doi-asserted-by":"publisher","first-page":"213","DOI":"10.1147\/rd.462.0213","volume":"46","author":"Y Taur","year":"2002","unstructured":"Taur, Y. (2002). CMOS design near the limit of scaling. IBM Journal of Research and Development, 46(2\/3), 213\u2013222.","journal-title":"IBM Journal of Research and Development"},{"key":"5428_CR4","doi-asserted-by":"crossref","unstructured":"Lin, L., & Burleson, W. (2009). Analysis and mitigation of process variation impacts on power-attack tolerance. In Proceedings of the 46th annual design automation conference (pp. 238\u2013243).","DOI":"10.1145\/1629911.1629977"},{"key":"5428_CR5","unstructured":"International Technology Roadmap for Semiconductors (ITRS). (2011). \n http:\/\/www.itrs.org\n \n ."},{"issue":"3","key":"5428_CR6","doi-asserted-by":"publisher","first-page":"654","DOI":"10.1109\/TED.2009.2039529","volume":"57","author":"R Vaddi","year":"2010","unstructured":"Vaddi, R., Dasgupta, S., & Agarwal, R. P. (2010). Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32\u00a0nm CMOS. IEEE Transactions on Electron Devices, 57(3), 654\u2013664.","journal-title":"IEEE Transactions on Electron Devices"},{"issue":"1","key":"5428_CR7","doi-asserted-by":"publisher","first-page":"67","DOI":"10.1109\/TCAD.2006.882491","volume":"26","author":"A Srivatsava","year":"2007","unstructured":"Srivatsava, A., Kachru, T., & Sylvester, D. (2007). Low-power-design space exploration considering process variation using robust optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(1), 67\u201379.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"4","key":"5428_CR8","doi-asserted-by":"publisher","first-page":"521","DOI":"10.1016\/j.sse.2003.09.021","volume":"48","author":"T Schulz","year":"2004","unstructured":"Schulz, T., Pacha, C., Luyken, R. J., St\u00e4dele, M., Hartwich, J., Dreeskornfeld, L., et al. (2004). Impact of technology parameters on device performance of UTB-SOI CMOS. Solid-State Electronics, 48(4), 521\u2013527.","journal-title":"Solid-State Electronics"},{"key":"5428_CR9","unstructured":"Berkeley Predictive Technology Model, University of California, Berkeley. (2004). (\n http:\/\/www.device.eecs.berkeley.edu\/~ptm\/\n \n )."},{"issue":"11","key":"5428_CR10","doi-asserted-by":"publisher","first-page":"2816","DOI":"10.1109\/TED.2006.884077","volume":"53","author":"W Zhao","year":"2006","unstructured":"Zhao, W., & Cao, Y. (2006). New generation of predictive technology model for sub-45\u00a0nm early design exploration. IEEE Transactions on Electron Devices, 53(11), 2816\u20132823.","journal-title":"IEEE Transactions on Electron Devices"},{"issue":"4","key":"5428_CR11","doi-asserted-by":"publisher","first-page":"305","DOI":"10.1561\/1000000012","volume":"3","author":"Y Cao","year":"2009","unstructured":"Cao, Y., Balijepalli, A., Sinha, S., Wang, C.-C., Wang, W., & Zhao, W. (2009). The predictive technology model in the late silicon era and beyond. Foundations and Trends in Electronic Design Automation, 3(4), 305\u2013401.","journal-title":"Foundations and Trends in Electronic Design Automation"},{"key":"5428_CR12","first-page":"90","volume-title":"Limits of gate-oxide scaling in nano-transistors","author":"B Yu","year":"2000","unstructured":"Yu, B., Wang, H., Riccobene, C., Xiang, Q., & Lin, M. R. (2000). Limits of gate-oxide scaling in nano-transistors (pp. 90\u201391). Honolulu: IEEE Symposium on VLSI Technology."},{"key":"5428_CR13","doi-asserted-by":"crossref","unstructured":"Sirisantana, N., Wei, L., & Roy, K. (2000). High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness. In Proceedings of international conference on computer design (pp. 227\u2013232).","DOI":"10.1109\/ICCD.2000.878290"},{"key":"5428_CR14","unstructured":"BSIM4.3.0 MOSFET Model\u2014User\u2019s manual. (2003). \n http:\/\/www-device.eecs.berkeley.edu\/bsim3\/~bsim4.html\n \n ."},{"key":"5428_CR15","doi-asserted-by":"publisher","DOI":"10.1002\/9780470823446","volume-title":"Compact MOSFET models for VLSI design","author":"AB Bhattacharyya","year":"2009","unstructured":"Bhattacharyya, A. B. (2009). Compact MOSFET models for VLSI design. New York: Wiley."}],"container-title":["Wireless Personal Communications"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11277-018-5428-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11277-018-5428-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11277-018-5428-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,2,22]],"date-time":"2019-02-22T20:34:29Z","timestamp":1550867669000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11277-018-5428-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2,23]]},"references-count":15,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2018,11]]}},"alternative-id":["5428"],"URL":"https:\/\/doi.org\/10.1007\/s11277-018-5428-8","relation":{},"ISSN":["0929-6212","1572-834X"],"issn-type":[{"value":"0929-6212","type":"print"},{"value":"1572-834X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,2,23]]},"assertion":[{"value":"23 February 2018","order":1,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}