{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,21]],"date-time":"2025-01-21T05:09:32Z","timestamp":1737436172456,"version":"3.33.0"},"reference-count":60,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2007,8,16]],"date-time":"2007-08-16T00:00:00Z","timestamp":1187222400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst Sign Image"],"published-print":{"date-parts":[[2008,2]]},"DOI":"10.1007\/s11265-007-0126-x","type":"journal-article","created":{"date-parts":[[2007,8,15]],"date-time":"2007-08-15T18:50:17Z","timestamp":1187203817000},"page":"231-249","source":"Crossref","is-referenced-by-count":4,"title":["Configurable Data Memory for Multimedia Processing"],"prefix":"10.1007","volume":"50","author":[{"given":"Eero","family":"Aho","sequence":"first","affiliation":[]},{"given":"Jarno","family":"Vanne","sequence":"additional","affiliation":[]},{"given":"Timo D.","family":"H\u00c4m\u00c4l\u00c4inen","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2007,8,16]]},"reference":[{"issue":"1","key":"126_CR1","doi-asserted-by":"crossref","first-page":"9","DOI":"10.1007\/s11265-005-6247-1","volume":"41","author":"H.-J. Stolberg","year":"2005","unstructured":"H.-J. Stolberg, M. Berekovic, S. Moch, L. Friebe, M.B. Kulaczewski, S. Fl\u00fcgel, H. Klu\u00dfmann, A. Dehnhardt and P. Pirsch, \u201cHiBRID-SoC: A Multi-Core SoC Architecture for Multimedia,\u201d J. VLSI Signal Process., vol. 41, no. 1, 2005, pp. 9\u201320.","journal-title":"J. VLSI Signal Process."},{"key":"126_CR2","doi-asserted-by":"crossref","unstructured":"P. Ranganathan, S. Adve and N.P. Jouppi, \u201cPerformance of Image and Video Processing with General-purpose Processors and Media ISA Extensions,\u201d in Proc. Int. Symp. Computer Architecture, Atlanta, GA, USA, 1999, pp. 124\u2013135, May.","DOI":"10.1109\/ISCA.1999.765945"},{"issue":"11","key":"126_CR3","doi-asserted-by":"crossref","first-page":"1317","DOI":"10.1109\/TC.2002.1047756","volume":"51","author":"N. Slingerland","year":"2002","unstructured":"N. Slingerland and A. J. Smith, \u201cMeasuring the Performance of Multimedia Instruction Sets,\u201d IEEE Trans. Comput., vol. 51, no. 11, 2002, pp. 1317\u20131332.","journal-title":"IEEE Trans. Comput."},{"key":"126_CR4","volume-title":"Computer Architecture: A Quantitative Approach","author":"J.L. Hennessy","year":"2003","unstructured":"J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, 3rd ed., Morgan Kaufman Publishers, 2003.","edition":"3"},{"key":"126_CR5","first-page":"63","volume-title":"Domain-specific Multiprocessors\u2014Systems, Architectures, Modeling, and Simulation","author":"J. Takala","year":"2004","unstructured":"J. Takala and T. J\u00e4rvinen, \u201cStride Permutation Access in Interleaved Memory Systems,\u201d in Domain-specific Multiprocessors\u2014Systems, Architectures, Modeling, and Simulation, S. S. Bhattacharyya, E. F. Deprettere, and J. Teich (Eds.), Marcel Dekker, 2004, pp. 63\u201384."},{"issue":"7","key":"126_CR6","first-page":"1674","volume":"E87-D","author":"E. Aho","year":"2004","unstructured":"E. Aho, J. Vanne, K. Kuusilinna and T.D. H\u00e4m\u00e4l\u00e4inen, \u201cAddress Computation in Configurable Parallel Memory Architecture,\u201d IEICE Trans. Inf. Syst., vol. E87-D, no. 7, 2004, pp. 1674\u20131681.","journal-title":"IEICE Trans. Inf. Syst."},{"issue":"12","key":"126_CR7","doi-asserted-by":"crossref","first-page":"1566","DOI":"10.1109\/T-C.1971.223171","volume":"C-20","author":"P. Budnik","year":"1971","unstructured":"P. Budnik and D.J. Kuck, \u201cThe Organization and Use of Parallel Memories,\u201d IEEE Trans. Comput., vol. C-20, no. 12, 1971, pp. 1566\u20131569.","journal-title":"IEEE Trans. Comput."},{"key":"126_CR8","doi-asserted-by":"crossref","unstructured":"S. Chen, A. Postula, and L. Jozwiak, \u201cSynthesis of XOR Storage Schemes with Different Cost for Minimization of Memory Contention,\u201d in Proc. Euromicro Conf., Milan, Italy, 1999, pp. 170\u2013177, Sep.","DOI":"10.1109\/EURMIC.1999.794463"},{"issue":"2","key":"126_CR9","doi-asserted-by":"crossref","first-page":"315","DOI":"10.1109\/TMM.2005.864345","volume":"8","author":"G. Kuzmanov","year":"2006","unstructured":"G. Kuzmanov, G. Gaydadjiev, and S. Vassiliadis, \u201cMultimedia Rectangularly Addressable Memory,\u201d IEEE Trans. Multimedia, vol. 8, no. 2, 2006, pp. 315\u2013322.","journal-title":"IEEE Trans. Multimedia"},{"key":"126_CR10","unstructured":"A. Norton and E. Melton, \u201cA Class of Boolean Linear Transformations for Conflict-Free Power-of-Two Stride Access,\u201d in Proc. Int. Conf. Parallel Processing, University Park, PA, USA, 1987, pp. 247\u2013254, Aug."},{"issue":"5","key":"126_CR11","doi-asserted-by":"crossref","first-page":"634","DOI":"10.1109\/12.381949","volume":"44","author":"M. Valero","year":"1995","unstructured":"M. Valero, T. Lang, M. Peiron, and E. Ayguad\u00e9, \u201cConflict-free Access for Streams in Multimodule Memories,\u201d IEEE Trans. Comput., vol. 44, no. 5, 1995, pp. 634\u2013646.","journal-title":"IEEE Trans. Comput."},{"key":"126_CR12","doi-asserted-by":"crossref","unstructured":"C. Verdier, E. Boutillon, A. Lafage, and A. Demeure, \u201cAccess and Alignment of Arrays for a Bidimensional Parallel Memory,\u201d in Proc. Int. Conf. Application Specific Array Processors, San Francisco, CA, USA, 1994, pp. 346\u2013356, Aug.","DOI":"10.1109\/ASAP.1994.331790"},{"issue":"1","key":"126_CR13","doi-asserted-by":"crossref","first-page":"75","DOI":"10.1109\/12.559804","volume":"46","author":"R. S. Katti","year":"1997","unstructured":"R. S. Katti, \u201cNonprime Memory Systems and Error Correction in Address Translation,\u201d IEEE Trans. Comput., vol. 46, no. 1, 1997, pp. 75\u201379.","journal-title":"IEEE Trans. Comput."},{"issue":"5","key":"126_CR14","doi-asserted-by":"crossref","first-page":"755","DOI":"10.1109\/TCOMM.2005.847158","volume":"53","author":"T. J\u00e4rvinen","year":"2005","unstructured":"T. J\u00e4rvinen, P. Salmela, T. Sipil\u00e4, and J. Takala, \u201cSystematic Approach for Path Metric Access in Viterbi Decoders,\u201d IEEE Trans. Commun., vol. 53, no. 5, 2005, pp. 755\u2013759.","journal-title":"IEEE Trans. Commun."},{"issue":"3","key":"126_CR15","doi-asserted-by":"crossref","first-page":"276","DOI":"10.1109\/12.76404","volume":"40","author":"D. T. Harper III","year":"1991","unstructured":"D. T. Harper III and D. A. Linebarger, \u201cConflict-free Vector Access Using a Dynamic Storage Scheme,\u201d IEEE Trans. Comput., vol. 40, no. 3, 1991, pp. 276\u2013283.","journal-title":"IEEE Trans. Comput."},{"issue":"2","key":"126_CR16","doi-asserted-by":"crossref","first-page":"227","DOI":"10.1109\/12.123399","volume":"41","author":"D. T. Harper III","year":"1992","unstructured":"D. T. Harper III, \u201cIncreased Memory Performance During Vector Accesses Through the Use of Linear Address Transformations,\u201d IEEE Trans. Comput., vol. 41, no. 2, 1992, pp. 227\u2013230.","journal-title":"IEEE Trans. Comput."},{"issue":"12","key":"126_CR17","doi-asserted-by":"crossref","first-page":"2717","DOI":"10.1109\/TCSI.2005.856894","volume":"52","author":"E. Aho","year":"2005","unstructured":"E. Aho, J. Vanne, T.D. H\u00e4m\u00e4l\u00e4inen and K. Kuusilinna, \u201cBlock-level Parallel Processing for Scaling Evenly Divisible Images,\u201d IEEE Trans. Circuits Syst. I, vol. 52, no. 12, 2005, pp. 2717\u20132725.","journal-title":"IEEE Trans. Circuits Syst. I"},{"key":"126_CR18","doi-asserted-by":"crossref","unstructured":"E. Aho, J. Vanne and T.D. H\u00e4m\u00e4l\u00e4inen, \u201cParallel Memory Architecture for Arbitrary Stride Accesses,\u201d in Proc. IEEE Workshop Design and Diagnostics of Electronic Circuits and Systems, Prague, Czech Republic, 2006, pp. 65\u201370, Apr.","DOI":"10.1109\/ICSAMOS.2006.300801"},{"key":"126_CR19","doi-asserted-by":"crossref","unstructured":"E. Aho, J. Vanne and T.D. H\u00e4m\u00e4l\u00e4inen, \u201cParallel Memory Implementation for Arbitrary Stride Accesses,\u201d in Proc. Embedded Computer Systems: Architectures, Modeling, and Simulation Conference, Samos, Greece, 2006, pp. 1\u20136, July.","DOI":"10.1109\/ICSAMOS.2006.300801"},{"issue":"3","key":"126_CR20","doi-asserted-by":"crossref","first-page":"157","DOI":"10.1023\/A:1012275211807","volume":"29","author":"P. Pirsch","year":"2001","unstructured":"P. Pirsch, C. Reuter, J.P. Wittenburg, M.B. Kulaczewski and H.-J. Stolberg, \u201cArchitecture Concepts for Multimedia Signal Processing,\u201d J. VLSI Signal Process., vol. 29, no. 3, 2001, pp. 157\u2013165.","journal-title":"J. VLSI Signal Process."},{"issue":"2","key":"126_CR21","doi-asserted-by":"crossref","first-page":"59","DOI":"10.1109\/79.664698","volume":"15","author":"P. Faraboschi","year":"1998","unstructured":"P. Faraboschi, G. Desoli and J.A. Fisher, \u201cThe Latest Word in Digital and Media Processing,\u201d IEEE Signal Process. Mag., vol. 15, no. 2, 1998, pp. 59\u201385.","journal-title":"IEEE Signal Process. Mag."},{"key":"126_CR22","doi-asserted-by":"crossref","unstructured":"D. Talla, L.K. John, V. Lapinskii and B.L. Evans, \u201cEvaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures,\u201d in Proc. Int. Conf. Computer Design, Austin, TX, USA, 2000, pp. 163\u2013172, Sep.","DOI":"10.1109\/ICCD.2000.878283"},{"issue":"1","key":"126_CR23","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/TVLSI.2004.840415","volume":"13","author":"D. Cheresiz","year":"1996","unstructured":"D. Cheresiz, B. Juurlink, S. Vassiliadis and H.A.G. Wijshoff, \u201cThe CSI Multimedia Architecture,\u201d IEEE Trans. VLSI Syst., vol. 13, no. 1, 2005, pp. 1\u201313.","journal-title":"IEEE Trans. VLSI Syst."},{"issue":"4","key":"126_CR24","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1109\/40.526924","volume":"16","author":"A. Peleg","year":"1996","unstructured":"A. Peleg and U. Weiser, \u201cMMX Technology Extension to the Intel Architecture,\u201d IEEE MICRO, vol. 16, no. 4, 1996, pp. 42\u201350.","journal-title":"IEEE MICRO"},{"issue":"12","key":"126_CR25","doi-asserted-by":"crossref","first-page":"26","DOI":"10.1109\/2.809248","volume":"32","author":"S. Thakkar","year":"1999","unstructured":"S. Thakkar and T. Huff, \u201cInternet Streaming SIMD Extensions,\u201d IEEE Computer, vol. 32, no. 12, 1999, pp. 26\u201334.","journal-title":"IEEE Computer"},{"issue":"1","key":"126_CR26","first-page":"1","volume":"8","author":"D. Boggs","year":"2004","unstructured":"D. Boggs, A. Baktha, J. Hawkins, D.T. Marr, J. A. Miller, P. Roussel, R. Singhal, B. Toll and K.S. Venkatraman, \u201cThe Microarchitecture of the Intel\u00ae Pentium\u00ae 4 Processor on 90\u00a0nm Technology,\u201d Intel Technol. J., vol. 8, no. 1, 2004, pp. 1\u201317.","journal-title":"Intel Technol. J."},{"issue":"2","key":"126_CR27","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1109\/40.755466","volume":"19","author":"S. Oberman","year":"1999","unstructured":"S. Oberman, G. Favor and F. Weber, \u201cAMD 3DNow! Technology: Architecture and Implementations,\u201d IEEE MICRO, vol. 19, no. 2, 1999, pp. 37\u201348.","journal-title":"IEEE MICRO"},{"issue":"4","key":"126_CR28","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/40.526921","volume":"16","author":"M. Tremblay","year":"1996","unstructured":"M. Tremblay, J.M. O\u2019Connor, V. Narayanan and L. He, \u201cVIS Speeds New Media Processing,\u201d IEEE MICRO, vol. 16, no. 4, 1996, pp. 10\u201320.","journal-title":"IEEE MICRO"},{"issue":"11","key":"126_CR29","doi-asserted-by":"crossref","first-page":"1618","DOI":"10.1109\/4.641681","volume":"32","author":"D.A. Carlson","year":"1997","unstructured":"D.A. Carlson, R.W. Castelino and R.O. Mueller, \u201cMultimedia Extensions for a 550-MHz RISC Microprocessor,\u201d IEEE J. Solid-State Circuits, vol. 32, no. 11, 1997, pp. 1618\u20131624.","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"4","key":"126_CR30","doi-asserted-by":"crossref","first-page":"51","DOI":"10.1109\/40.526925","volume":"16","author":"R.B. Lee","year":"1996","unstructured":"R.B. Lee, \u201cSubword Parallelism with MAX-2,\u201d IEEE MICRO, vol. 16, no. 4, 1996, pp. 51\u201359.","journal-title":"IEEE MICRO"},{"issue":"2","key":"126_CR31","doi-asserted-by":"crossref","first-page":"85","DOI":"10.1109\/40.848475","volume":"20","author":"K. Diefendorff","year":"2000","unstructured":"K. Diefendorff, P.K. Dubey, R. Hochsprung and H. Scale, \u201cAltiVec Extension to PowerPC Accelerates Media Processing,\u201d IEEE MICRO, vol. 20, no. 2, 2000, pp. 85\u201395.","journal-title":"IEEE MICRO"},{"issue":"1","key":"126_CR32","doi-asserted-by":"crossref","first-page":"66","DOI":"10.1109\/40.820055","volume":"20","author":"J. Fridman","year":"2000","unstructured":"J. Fridman and Z. Greenfield, \u201cThe TigerSHARC DSP Architecture,\u201d IEEE MICRO, vol. 20, no. 1, 2000, pp. 66\u201376.","journal-title":"IEEE MICRO"},{"key":"126_CR33","unstructured":"Texas Instruments, Inc., TMS320C64x Technical Overview, Texas Instruments, Inc., 2001, Jan."},{"issue":"8","key":"126_CR34","doi-asserted-by":"crossref","first-page":"646","DOI":"10.1109\/TCSVT.2002.800864","volume":"12","author":"C. Basoglu","year":"2002","unstructured":"C. Basoglu, W. Lee and J. O\u2019Donnell, \u201cThe Equator MAP-CA\u2122 DSP: An End-to-End Broadband Signal Processor\u2122 VLIW,\u201d IEEE Trans. Circuits Syst. Video Technol., vol. 12, no. 8, 2002, pp. 646\u2013659.","journal-title":"IEEE Trans. Circuits Syst. Video Technol."},{"key":"126_CR35","doi-asserted-by":"crossref","unstructured":"J.-W. van de Waerdt, S. Vassiliadis, S. Das, S. Mirolo, C. Yen, B. Zhong, C. Basto, J.-P. van Itegem, D. Amirtharaj, K. Kalra, P. Rodriguez, and H. van Antwerpen, \u201cThe TM3270 Media-Processor,\u201d in Proc. IEEE\/ACM Int. Symp. Microarchitecture, Barcelona, Spain, 2005, pp. 331\u2013342, Nov.","DOI":"10.1109\/MICRO.2005.35"},{"issue":"8","key":"126_CR36","doi-asserted-by":"crossref","first-page":"660","DOI":"10.1109\/TCSVT.2002.800865","volume":"12","author":"V. Lappalainen","year":"2002","unstructured":"V. Lappalainen, T.D. H\u00e4m\u00e4l\u00e4inen and P. Liuha, \u201cOverview of Research Efforts on Media ISA Extensions and Their Usage in Video Coding,\u201d IEEE Trans. Circuits Syst. Video Technol., vol. 12, no. 8, 2002, pp. 660\u2013670.","journal-title":"IEEE Trans. Circuits Syst. Video Technol."},{"key":"126_CR37","doi-asserted-by":"crossref","unstructured":"J. Corbal, M. Valero and R. Espasa, \u201cExploiting a New Level of DLP in Multimedia Applications,\u201d in Proc. Int. Symp. Microarchitecture, Haifa, Israel, 1999, pp. 72\u201379, Nov.","DOI":"10.1109\/MICRO.1999.809445"},{"issue":"11","key":"126_CR38","doi-asserted-by":"crossref","first-page":"1117","DOI":"10.1109\/12.966490","volume":"50","author":"L. Zhang","year":"2001","unstructured":"L. Zhang, Z. Fang, M. Parker, B.K. Mathew, L. Schaelicke, J.B. Carter, W. C. Hsieh and S.A. McKee, \u201cThe Impulse Memory Controller,\u201d IEEE Trans. Comput., vol. 50, no. 11, 2001, pp. 1117\u20131132.","journal-title":"IEEE Trans. Comput."},{"issue":"11","key":"126_CR39","doi-asserted-by":"crossref","first-page":"1255","DOI":"10.1109\/12.895941","volume":"49","author":"S.A. McKee","year":"2000","unstructured":"S. A. McKee, W. A. Wulf, J. H. Aylor, R. H. Klenke, M. H. Salinas, S. I. Hong, and D. A. B. Weikle, \u201cDynamic Access Ordering for Streamed Computations,\u201d IEEE Trans. Comput., vol. 49, no. 11, 2000, pp. 1255\u20131271.","journal-title":"IEEE Trans. Comput."},{"issue":"2","key":"126_CR40","doi-asserted-by":"crossref","first-page":"35","DOI":"10.1109\/40.918001","volume":"21","author":"B. Khailany","year":"2001","unstructured":"B. Khailany, W. J. Dally, U. J. Kapasi, P. Mattson, J. Namkoong, J. D. Owens, B. Towles, A. Chang, and Scott Rixner, \u201cImagine: Media Processing with Streams,\u201d IEEE MICRO, vol. 21, no. 2, 2001, pp. 35\u201346.","journal-title":"IEEE MICRO"},{"issue":"6","key":"126_CR41","doi-asserted-by":"crossref","first-page":"36","DOI":"10.1109\/MM.2003.1261385","volume":"23","author":"C. E. Kozyrakis","year":"2003","unstructured":"C. E. Kozyrakis and D. A. Patterson, \u201cScalable Vector Processors for Embedded Systems,\u201d IEEE MICRO, vol. 23, no. 6, 2003, pp. 36\u201345.","journal-title":"IEEE MICRO"},{"issue":"12","key":"126_CR42","doi-asserted-by":"crossref","first-page":"1329","DOI":"10.1109\/71.334907","volume":"5","author":"A. Seznec","year":"1994","unstructured":"A. Seznec and J. Lenfant, \u201cInterleaved Parallel Schemes,\u201d IEEE Trans. Parallel Distrib. Syst., vol. 5, no. 12, 1994, pp. 1329\u20131334.","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"126_CR43","unstructured":"J.M. Frailong, W. Jalby and J. Lenfant, \u201cXOR-Schemes: A Flexible Data Organization in Parallel Memories,\u201d in Proc. Int\u2019l Conf. Parallel Processing, Washington, DC, USA, 1985, pp. 276\u2013283, Aug."},{"key":"126_CR44","doi-asserted-by":"crossref","unstructured":"K. Kim and V.K. Prasanna Kumar, \u201cParallel Memory Systems for Image Processing,\u201d in Proc. IEEE Conf. Computer Vision and Pattern Recognition, San Diego, CA, USA, 1989, pp. 654\u2013659, June.","DOI":"10.1109\/CVPR.1989.37915"},{"issue":"12","key":"126_CR45","doi-asserted-by":"crossref","first-page":"1145","DOI":"10.1109\/T-C.1975.224157","volume":"C-24","author":"D.H. Lawrie","year":"1975","unstructured":"D.H. Lawrie, \u201cAccess and Alignment of Data in an Array Processor,\u201d IEEE Trans. Comput., vol. C-24, no. 12, 1975, pp. 1145\u20131155.","journal-title":"IEEE Trans. Comput."},{"issue":"2","key":"126_CR46","doi-asserted-by":"crossref","first-page":"233","DOI":"10.1109\/TC.1987.1676887","volume":"C-36","author":"H.A.G. Wijshoff","year":"1987","unstructured":"H.A.G. Wijshoff and J. van Leeuwen, \u201cOn Linear Skewing Schemes and d-ordered Vectors,\u201d IEEE Trans. Comput., vol. C-36, no. 2, 1987, pp. 233\u2013239.","journal-title":"IEEE Trans. Comput."},{"issue":"1","key":"126_CR47","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1016\/0020-0190(89)90180-4","volume":"33","author":"D.-L. Lee","year":"1989","unstructured":"D.-L. Lee, \u201cOn Access and Alignment of Data in a Parallel Processor,\u201d Inf. Process. Lett., vol. 33, no. 1, 1989, pp. 11\u201314.","journal-title":"Inf. Process. Lett."},{"key":"126_CR48","unstructured":"D.T. Harper III and D.A. Linebarger, \u201cDynamic Address Mapping for Conflict-Free Vector Access,\u201d U.S. Patent 4 918 600, Apr 17, 1990."},{"issue":"1","key":"126_CR49","doi-asserted-by":"crossref","first-page":"36","DOI":"10.1109\/76.660828","volume":"8","author":"S. Dutta","year":"1998","unstructured":"S. Dutta, W. Wolf and A. Wolfe, \u201cA Methodology to Evaluate Memory Architecture Design Tradeoffs for Video Signal Processors,\u201d IEEE Trans. Circuits Syst. Video Technol., vol. 8, no. 1, 1998, pp. 36\u201353.","journal-title":"IEEE Trans. Circuits Syst. Video Technol."},{"key":"126_CR50","unstructured":"Altera, Stratix Device Handbook, vol. 1, version 3.2, Altera, 2005. Jan."},{"key":"126_CR51","unstructured":"Altera, Nios 3.0 CPU Data Sheet, version 2.2, Altera, 2004, Oct."},{"key":"126_CR52","doi-asserted-by":"crossref","unstructured":"E. Salminen, A. Kulmala and T.D. H\u00e4m\u00e4l\u00e4inen, \u201cHIBI-based Multiprocessor SoC on FPGA,\u201d in Proc. IEEE Int\u2019l Symp. Circuits Syst., Kobe, Japan, 2005, pp. 3351\u20133354, May.","DOI":"10.1109\/ISCAS.2005.1465346"},{"issue":"5","key":"126_CR53","doi-asserted-by":"crossref","first-page":"283","DOI":"10.1016\/j.micpro.2006.09.003","volume":"31","author":"E. Aho","year":"2007","unstructured":"E. Aho, J. Vanne, T.D. H\u00e4m\u00e4l\u00e4inen and K. Kuusilinna, \u201cConfigurable Implementation of Parallel Memory Based Real-time Video Downscaler,\u201d Microprocess. Microsyst., vol. 31, no. 5, 2007, pp. 283\u2013292.","journal-title":"Microprocess. Microsyst."},{"key":"126_CR54","doi-asserted-by":"crossref","unstructured":"L. Li, S. Goto and T. Ikenaga, \u201cAn Efficient Deblocking Filter Architecture with 2-Dimensional Parallel Memory for H.264\/AVC,\u201d in Proc. Asia and South Pacific Design Automation Conf., Shanghai, China, 2005, pp. 623\u2013626, Jan.","DOI":"10.1145\/1120725.1120978"},{"key":"126_CR55","doi-asserted-by":"crossref","unstructured":"J. Vanne, E. Aho, T.D. H\u00e4m\u00e4l\u00e4inen and K. Kuusilinna, \u201cA Parallel Memory System for Variable Block Size Motion Estimation Algorithms,\u201d IEEE Trans. Circuits Syst. Video Technol. (in press).","DOI":"10.1109\/TCSVT.2008.918273"},{"key":"126_CR56","unstructured":"T.H. Morrin and D.C. van Voorhis, \u201cMethod and Apparatus for Accessing Horizontal Sequences and Rectangular Sub-Arrays from an Array Stored in a Modified Word Organized Random Access Memory System,\u201d U.S. Patent 3 938 102, Feb 10, 1976."},{"issue":"7","key":"126_CR57","doi-asserted-by":"crossref","first-page":"669","DOI":"10.1109\/TC.1986.1676813","volume":"C-35","author":"J.W. Park","year":"1986","unstructured":"J.W. Park, \u201cAn Efficient Memory System for Image Processing,\u201d IEEE Trans. Comput., vol. C-35, no. 7, 1986, pp. 669\u2013674.","journal-title":"IEEE Trans. Comput."},{"issue":"11","key":"126_CR58","doi-asserted-by":"crossref","first-page":"1270","DOI":"10.1109\/TCSVT.2004.835148","volume":"14","author":"J.K. Tanskanen","year":"2004","unstructured":"J. K. Tanskanen, T. Sihvo, and J. Niittylahti, \u201cByte and Modulo Addressable Parallel Memory Architecture for Video Coding,\u201d IEEE Trans. Circuits Syst. Video Technol., vol. 14, no. 11, 2004, pp. 1270\u20131276.","journal-title":"IEEE Trans. Circuits Syst. Video Technol."},{"issue":"2","key":"126_CR59","doi-asserted-by":"crossref","first-page":"215","DOI":"10.1007\/s11265-005-4962-2","volume":"40","author":"J. K. Tanskanen","year":"2005","unstructured":"J.K. Tanskanen, R. Creutzburg, and J.T. Niittylahti, \u201cOn Design of Parallel Memory Access Schemes for Video Coding,\u201d J. VLSI Signal Process., vol. 40, no. 2, 2005, pp. 215\u2013237.","journal-title":"J. VLSI Signal Process."},{"issue":"2","key":"126_CR60","doi-asserted-by":"crossref","first-page":"173","DOI":"10.1023\/B:VLSI.0000040428.04740.fe","volume":"38","author":"J.K. Tanskanen","year":"2004","unstructured":"J.K. Tanskanen and J.T. Niittylahti, \u201cScalable Parallel Memory Architectures for Video Coding,\u201d J. VLSI Signal Process., vol. 38, no. 2, 2004, pp. 173\u2013199.","journal-title":"J. VLSI Signal Process."}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-007-0126-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-007-0126-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-007-0126-x","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T10:57:51Z","timestamp":1737370671000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-007-0126-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,8,16]]},"references-count":60,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2008,2]]}},"alternative-id":["126"],"URL":"https:\/\/doi.org\/10.1007\/s11265-007-0126-x","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"type":"print","value":"1939-8018"},{"type":"electronic","value":"1939-8115"}],"subject":[],"published":{"date-parts":[[2007,8,16]]}}}