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The problem causes logically independent cores to affect each other\u2019s performance, leading to pessimistic worst-case execution time analysis. Memory regulation via throttling is one of the most practical techniques to mitigate interference. Traditional regulation schemes rely on a combination of timer and performance counter interrupts to be delivered and processed on the same cores running real-time workload. Unfortunately, to prevent excessive overhead, regulation can only be enforced at a millisecond-scale granularity. In this work, we present a novel regulation mechanism from outside the cores<\/jats:italic> that monitors performance counters for the application core\u2019s activity in main memory at a microsecond scale. The approach is fully transparent to the applications on the cores, and can be implemented using widely available on-chip debug facilities. The presented mechanism also allows more complex composition of metrics to enact load-aware regulation. For instance, it allows redistributing unused bandwidth between cores while keeping the overall memory bandwidth of all cores below a given threshold. We implement our approach on a host of embedded platforms and conduct an in-depth evaluation on the Xilinx Zynq UltraScale+ ZCU102, NXP i.MX8M and NXP S32G2 platforms using the San Diego Vision Benchmark Suite.<\/jats:p>","DOI":"10.1007\/s11241-024-09422-8","type":"journal-article","created":{"date-parts":[[2024,6,17]],"date-time":"2024-06-17T16:02:53Z","timestamp":1718640173000},"page":"369-412","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["MemPol: polling-based microsecond-scale per-core memory bandwidth regulation"],"prefix":"10.1007","volume":"60","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0134-318X","authenticated-orcid":false,"given":"Alexander","family":"Zuepke","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8256-6160","authenticated-orcid":false,"given":"Andrea","family":"Bastoni","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0009-0002-4856-0421","authenticated-orcid":false,"given":"Weifan","family":"Chen","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2328-044X","authenticated-orcid":false,"given":"Marco","family":"Caccamo","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3558-5216","authenticated-orcid":false,"given":"Renato","family":"Mancuso","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2024,6,17]]},"reference":[{"doi-asserted-by":"publisher","unstructured":"Agrawal A, Fohler G, Freitag J, Nowotsch J, Uhrig S, Paulitsch M (2017) Contention-aware dynamic memory bandwidth isolation with predictability in COTS multicores: an avionics case study. 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