{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,1,24]],"date-time":"2024-01-24T15:40:12Z","timestamp":1706110812948},"reference-count":46,"publisher":"Springer Science and Business Media LLC","issue":"5","license":[{"start":{"date-parts":[[2022,12,18]],"date-time":"2022-12-18T00:00:00Z","timestamp":1671321600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2022,12,18]],"date-time":"2022-12-18T00:00:00Z","timestamp":1671321600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2023,5]]},"DOI":"10.1007\/s00034-022-02237-7","type":"journal-article","created":{"date-parts":[[2022,12,18]],"date-time":"2022-12-18T06:02:10Z","timestamp":1671343330000},"page":"2828-2851","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI\/ML Applications"],"prefix":"10.1007","volume":"42","author":[{"ORCID":"http:\/\/orcid.org\/0000-0002-8254-6378","authenticated-orcid":false,"given":"Abhash","family":"Kumar","sequence":"first","affiliation":[]},{"given":"Sai Manohar","family":"Beeraka","sequence":"additional","affiliation":[]},{"given":"Jawar","family":"Singh","sequence":"additional","affiliation":[]},{"given":"Bharat","family":"Gupta","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2022,12,18]]},"reference":[{"issue":"3","key":"2237_CR1","doi-asserted-by":"publisher","first-page":"215","DOI":"10.1147\/rd.413.0215","volume":"41","author":"PG Emma","year":"1997","unstructured":"P.G. Emma, Understanding some simple processor-performance limits. IBM J. Res. Dev. 41(3), 215\u2013232 (1997)","journal-title":"IBM J. Res. Dev."},{"issue":"1","key":"2237_CR2","doi-asserted-by":"publisher","first-page":"3","DOI":"10.1016\/0925-2312(93)90019-Y","volume":"5","author":"Y Hirai","year":"1993","unstructured":"Y. Hirai, Hardware implementation of neural networks in Japan. Neurocomputing 5(1), 3\u201316 (1993)","journal-title":"Neurocomputing"},{"key":"2237_CR3","doi-asserted-by":"crossref","unstructured":"B. Moons and M. Verhelst, A 0.3\u20132.6 TOPS\/W precision scalable processor for real-time large-scale ConvNets. in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits). IEEE (2016).","DOI":"10.1109\/VLSIC.2016.7573525"},{"key":"2237_CR4","doi-asserted-by":"crossref","unstructured":"B. Moons, et al., 14.5 envision: A 0.26-to-10tops\/w subword-parallel dynamic-voltage-accuracy-frequency-scalable convolutional neural network processor in 28nm fdsoi. in 2017 IEEE International Solid-State Circuits Conference (ISSCC). IEEE (2017).","DOI":"10.1109\/ISSCC.2017.7870353"},{"key":"2237_CR5","doi-asserted-by":"crossref","unstructured":"M. Price, J. Glass and A.P. Chandrakasan, 14.4 A scalable speech recognizer with deep-neural-network acoustic models and voice-activated power gating. in 2017 IEEE International Solid-State Circuits Conference (ISSCC). IEEE (2017).","DOI":"10.1109\/ISSCC.2017.7870352"},{"key":"2237_CR6","doi-asserted-by":"crossref","unstructured":"P.N. Whatmough, et al., 14.3 A 28nm SoC with a 1.2 GHz 568nJ\/prediction sparse deep-neural-network engine with\u00bf 0.1 timing error rate tolerance for IoT applications. in 2017 IEEE International Solid-State Circuits Conference (ISSCC). IEEE (2017).","DOI":"10.1109\/ISSCC.2017.7870351"},{"issue":"3","key":"2237_CR7","doi-asserted-by":"publisher","first-page":"494","DOI":"10.1109\/JETCAS.2018.2829522","volume":"8","author":"M Kang","year":"2018","unstructured":"M. Kang et al., An in-memory VLSI architecture for convolutional neural networks. IEEE J. Emerg. Selected Topics Circuits Syst. 8(3), 494\u2013505 (2018)","journal-title":"IEEE J. Emerg. Selected Topics Circuits Syst."},{"key":"2237_CR8","doi-asserted-by":"crossref","unstructured":"M. Kang, S.K. Gonugondla, N.R. Shanbhag, A 19.4 nJ\/decision 364K decisions\/s in-memory random forest classifier in 6T SRAM array. in ESSCIRC 2017\u201343rd IEEE European Solid State Circuits Conference. IEEE, (2017).","DOI":"10.1109\/ESSCIRC.2017.8094576"},{"issue":"4","key":"2237_CR9","doi-asserted-by":"publisher","first-page":"915","DOI":"10.1109\/JSSC.2016.2642198","volume":"52","author":"J Zhang","year":"2017","unstructured":"J. Zhang, Z. Wang, N. Verma, In-memory computation of a machine-learning classifier in a standard 6T SRAM array. IEEE J. Solid-State Circuits 52(4), 915\u2013924 (2017)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"2","key":"2237_CR10","doi-asserted-by":"publisher","first-page":"1059","DOI":"10.1007\/s00034-019-01226-7","volume":"39","author":"K Karras","year":"2020","unstructured":"K. Karras et al., A hardware acceleration platform for AI-based inference at the edge. Circuits Syst. Signal Process. 39(2), 1059\u20131070 (2020)","journal-title":"Circuits Syst. Signal Process."},{"issue":"5","key":"2237_CR11","doi-asserted-by":"publisher","first-page":"2097","DOI":"10.1007\/s00034-018-0953-y","volume":"38","author":"UA Korat","year":"2019","unstructured":"U.A. Korat, A. Alimohammad, A reconfigurable hardware architecture for principal component analysis. Circuits Syst. Signal Process. 38(5), 2097\u20132113 (2019)","journal-title":"Circuits Syst. Signal Process."},{"issue":"10\u201312","key":"2237_CR12","doi-asserted-by":"publisher","first-page":"2171","DOI":"10.1016\/j.neucom.2008.06.027","volume":"72","author":"N Nedjah","year":"2009","unstructured":"N. Nedjah et al., Dynamic MAC-based architecture of artificial neural networks suitable for hardware implementation on FPGAs. Neurocomputing 72(10\u201312), 2171\u20132179 (2009)","journal-title":"Neurocomputing"},{"issue":"3","key":"2237_CR13","doi-asserted-by":"publisher","first-page":"1542","DOI":"10.1007\/s00034-020-01534-3","volume":"40","author":"M Panwar","year":"2021","unstructured":"M. Panwar et al., M2DA: a low-complex design methodology for convolutional neural network exploiting data symmetry and redundancy. Circuits Syst. Signal Process. 40(3), 1542\u20131567 (2021)","journal-title":"Circuits Syst. Signal Process."},{"issue":"3","key":"2237_CR14","doi-asserted-by":"publisher","first-page":"816","DOI":"10.1016\/j.nima.2007.08.163","volume":"581","author":"E Won","year":"2007","unstructured":"E. Won, A hardware implementation of artificial neural networks using field programmable gate arrays. Nucl. Instrum. Methods Phys. Res., Sect. A 581(3), 816\u2013820 (2007)","journal-title":"Nucl. Instrum. Methods Phys. Res., Sect. A"},{"issue":"1","key":"2237_CR15","doi-asserted-by":"publisher","first-page":"461","DOI":"10.1007\/s00034-021-01789-4","volume":"41","author":"SM Beeraka","year":"2022","unstructured":"S.M. Beeraka et al., Accuracy enhancement of epileptic seizure detection: a deep learning approach with hardware realization of STFT. Circuits Syst. Signal Process. 41(1), 461\u2013484 (2022)","journal-title":"Circuits Syst. Signal Process."},{"key":"2237_CR16","doi-asserted-by":"crossref","unstructured":"O. Krestinskaya, K.N. Salama, and A. P. James, Analog backpropagation learning circuits for memristive crossbar neural networks. in 2018 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, (2018).","DOI":"10.1109\/ISCAS.2018.8351344"},{"key":"2237_CR17","doi-asserted-by":"crossref","unstructured":"A.J. P\u00b4erez-Avila, et al., Multilevel memristor based matrix-vector \u00b4 multiplication: influence of the discretization method. in 2021 13th Spanish Conference on Electron Devices (CDE). IEEE (2021).","DOI":"10.1109\/CDE52135.2021.9455724"},{"key":"2237_CR18","doi-asserted-by":"crossref","unstructured":"W. Woods and C. Teuscher. Approximate vector matrix multiplication implementations for neuromorphic applications using memristive crossbars. In 2017 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE, (2017).","DOI":"10.1109\/NANOARCH.2017.8053729"},{"key":"2237_CR19","doi-asserted-by":"crossref","unstructured":"M.V. Nair, P. Dudek. Gradient-descent-based learning in memristive crossbar arrays. in 2015 International Joint Conference on Neural Networks (IJCNN). IEEE (2015).","DOI":"10.1109\/IJCNN.2015.7280658"},{"issue":"11","key":"2237_CR20","doi-asserted-by":"publisher","first-page":"1178","DOI":"10.1038\/81453","volume":"3","author":"LF Abbott","year":"2000","unstructured":"L.F. Abbott, S.B. Nelson, Synaptic plasticity: taming the beast. Nat. Neurosci. 3(11), 1178\u20131183 (2000)","journal-title":"Nat. Neurosci."},{"issue":"5544","key":"2237_CR21","doi-asserted-by":"publisher","first-page":"1030","DOI":"10.1126\/science.1067020","volume":"294","author":"ER Kandel","year":"2001","unstructured":"E.R. Kandel, The molecular biology of memory storage: a dialogue between genes and synapses. Science 294(5544), 1030\u20131038 (2001)","journal-title":"Science"},{"issue":"4","key":"2237_CR22","doi-asserted-by":"publisher","first-page":"335","DOI":"10.1038\/s41563-017-0001-5","volume":"17","author":"S Choi","year":"2018","unstructured":"S. Choi et al., SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations. Nature Mater. 17(4), 335\u2013340 (2018)","journal-title":"Nature Mater."},{"key":"2237_CR23","doi-asserted-by":"crossref","unstructured":"S. Park, et al., RRAM-based synapse for neuromorphic system with pattern recognition function. in 2012 International Electron Devices Meeting. IEEE (2012).","DOI":"10.1109\/IEDM.2012.6479016"},{"issue":"2","key":"2237_CR24","doi-asserted-by":"publisher","first-page":"917","DOI":"10.1109\/TED.2018.2888871","volume":"66","author":"Y-T Seo","year":"2019","unstructured":"Y.-T. Seo et al., Si-based FET-type synaptic device with short-term and long-term plasticity using high-\u03ba gate-stack. IEEE Trans. Electron. Devices 66(2), 917\u2013923 (2019)","journal-title":"IEEE Trans. Electron. Devices"},{"issue":"2","key":"2237_CR25","doi-asserted-by":"publisher","first-page":"642","DOI":"10.1109\/JSSC.2017.2782087","volume":"53","author":"M Kang","year":"2018","unstructured":"M. Kang et al., A multi-functional in-memory inference processor using a standard 6T SRAM array. IEEE J. Solid-State Circuits 53(2), 642\u2013655 (2018)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"2237_CR26","unstructured":"N. Shanbhag, M. Kang and M. S. Keel, Compute memory. US Patent US9697877B2.[Online]. Available: https:\/\/patentsgoogle.com\/-patent\/US9697877 (2017)."},{"issue":"11","key":"2237_CR27","doi-asserted-by":"publisher","first-page":"3163","DOI":"10.1109\/JSSC.2018.2867275","volume":"53","author":"SK Gonugondla","year":"2018","unstructured":"S.K. Gonugondla, M. Kang, N.R. Shanbhag, A variation-tolerant in-memory machine learning classifier via on-chip training. IEEE J. Solid-State Circuits 53(11), 3163\u20133173 (2018)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"2237_CR28","unstructured":"A. Kumar, et al., In-memory Implementation of On-chip Trainable and Scalable ANN for AI\/ML Applications. arXiv preprint arXiv:2005.09526 (2020)."},{"key":"2237_CR29","doi-asserted-by":"crossref","unstructured":"I. Tsmots, O. Skorokhoda, and V. Rabyk, Hardware implementation of sigmoid activation functions using FPGA. in 2019 IEEE 15th International Conference on the Experience of Designing and Application of CAD Systems (CADSM). IEEE (2019).","DOI":"10.1109\/CADSM.2019.8779253"},{"key":"2237_CR30","doi-asserted-by":"crossref","unstructured":"A.H. Namin, et al., Efficient hardware implementation of the hyperbolic tangent sigmoid function. in 2009 IEEE International Symposium on Circuits and Systems. IEEE (2009).","DOI":"10.1109\/ISCAS.2009.5118213"},{"key":"2237_CR31","doi-asserted-by":"crossref","unstructured":"I. Kouretas, and V. Paliouras. Simplified hardware implementation of the softmax activation function. in 2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST). IEEE, (2019).","DOI":"10.1109\/MOCAST.2019.8741677"},{"key":"2237_CR32","unstructured":"Predictive Technology Model. http:\/\/ptm.asu.edu\/"},{"issue":"2","key":"2237_CR33","doi-asserted-by":"publisher","first-page":"179","DOI":"10.1111\/j.1469-1809.1936.tb02137.x","volume":"7","author":"RA Fisher","year":"1936","unstructured":"R.A. Fisher, The use of multiple measurements in taxonomic problems. Ann. Eugen. 7(2), 179\u2013188 (1936)","journal-title":"Ann. Eugen."},{"key":"2237_CR34","unstructured":"Iris Dataset. https:\/\/archive.ics.uci.edu\/ml\/datasets\/iris"},{"issue":"6","key":"2237_CR35","doi-asserted-by":"publisher","first-page":"141","DOI":"10.1109\/MSP.2012.2211477","volume":"29","author":"Li Deng","year":"2012","unstructured":"Li. Deng, The mnist database of handwritten digit images for machine learning research [best of the web]. IEEE Signal Process. Mag. 29(6), 141\u2013142 (2012)","journal-title":"IEEE Signal Process. Mag."},{"key":"2237_CR36","doi-asserted-by":"crossref","unstructured":"A. Biswas, A.P. Chandrakasan, Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications. in 2018 IEEE International Solid-State Circuits Conference-(ISSCC). IEEE, (2018).","DOI":"10.1109\/ISSCC.2018.8310397"},{"key":"2237_CR37","doi-asserted-by":"crossref","unstructured":"W.-S. Khwa, et al., A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS\/W fully parallel product-sum operation for binary DNN edge processors. in 2018 IEEE International Solid-State Circuits Conference-(ISSCC). IEEE, (2018).","DOI":"10.1109\/ISSCC.2018.8310401"},{"issue":"1","key":"2237_CR38","doi-asserted-by":"publisher","first-page":"60","DOI":"10.1109\/JSSC.2019.2939888","volume":"55","author":"A Sayal","year":"2019","unstructured":"A. Sayal et al., A 12.08-TOPS\/W all-digital time-domain CNN engine using bi-directional memory delay lines for energy efficient edge computing. IEEE J. Solid-State Circuits 55(1), 60\u201375 (2019)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"3","key":"2237_CR39","doi-asserted-by":"publisher","first-page":"636","DOI":"10.1109\/JSSC.2018.2878830","volume":"54","author":"P Harpe","year":"2018","unstructured":"P. Harpe, A compact 10-b SAR ADC with unit-length capacitors and a passive FIR filter. IEEE J. Solid-State Circuits 54(3), 636\u2013645 (2018)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"2237_CR40","doi-asserted-by":"crossref","unstructured":"Choi, I., et al., An SRAM-based hybrid computation-in-memory macro using current-reused differential CCO. IEEE J. Emerg. Selected Topics Circuits Syst. (2022).","DOI":"10.1109\/JETCAS.2022.3170595"},{"issue":"10","key":"2237_CR41","doi-asserted-by":"publisher","first-page":"2730","DOI":"10.1109\/JSSC.2019.2926649","volume":"54","author":"Y Toyama","year":"2019","unstructured":"Y. Toyama et al., An 8 bit 12.4 TOPS\/W phase-domain MAC circuit for energy-constrained deep learning accelerators. IEEE J. Solid-State Circuits 54(10), 2730\u20132742 (2019)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"9","key":"2237_CR42","doi-asserted-by":"publisher","first-page":"2817","DOI":"10.1109\/JSSC.2021.3073254","volume":"56","author":"X Si","year":"2021","unstructured":"X. Si et al., A local computing cell and 6T SRAM-based computing in-memory macro with 8-b MAC operation for edge AI chips. IEEE J. Solid-State Circuits 56(9), 2817\u20132831 (2021)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"2237_CR43","unstructured":"H. Xiao, K. Rasul, and R. Vollgraf. Fashion-mnist: a novel image dataset for benchmarking machine learning algorithms. arXiv preprint arXiv:1708.07747 (2017)."},{"key":"2237_CR44","unstructured":"D. Robinson, Comparing pairs of mnist digits based on one pixel. Github. https:\/\/gist.github.com\/dgrtwo\/aaef94ecc6a60cd50322c0054cc04478"},{"key":"2237_CR45","unstructured":"I. Goodfellow Instead of moving on to harder datasets than mnist, the ML community is studying it more than ever. even proportional to other datasets https:\/\/t.co\/tao52vc1fg. Twitter (2017). https:\/\/twitter.com\/goodfellowian\/status\/852591106655043584"},{"key":"2237_CR46","unstructured":"F. Cholle, Many good ideas will not work well on MNIST. Twitter (2017). https:\/\/twitter.com\/fchollet\/status\/852594987527045120"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-022-02237-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s00034-022-02237-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-022-02237-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,4,15]],"date-time":"2023-04-15T04:47:38Z","timestamp":1681534058000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s00034-022-02237-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,12,18]]},"references-count":46,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2023,5]]}},"alternative-id":["2237"],"URL":"https:\/\/doi.org\/10.1007\/s00034-022-02237-7","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,12,18]]},"assertion":[{"value":"11 February 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"7 November 2022","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"8 November 2022","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"18 December 2022","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare that they have no conflict of interest.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}},{"value":"This article does not contain any studies with human participants or animals performed by any of the authors.","order":3,"name":"Ethics","group":{"name":"EthicsHeading","label":"Ethical approval"}}]}}