{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,22]],"date-time":"2024-12-22T16:40:08Z","timestamp":1734885608384,"version":"3.32.0"},"reference-count":21,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[1995,2,1]],"date-time":"1995-02-01T00:00:00Z","timestamp":791596800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[1995,2]]},"DOI":"10.1007\/bf00993130","type":"journal-article","created":{"date-parts":[[2005,1,14]],"date-time":"2005-01-14T17:55:23Z","timestamp":1105725323000},"page":"59-73","source":"Crossref","is-referenced-by-count":2,"title":["A switch-level test generation system for synchronous and asynchronous circuits"],"prefix":"10.1007","volume":"6","author":[{"given":"Kent L.","family":"Einspahr","sequence":"first","affiliation":[]},{"given":"Sharad C.","family":"Seth","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"CR1","unstructured":"P. Agrawal and S.M. Reddy, ?Test Generation at MOS Level,?Proc. Int'l Conf. on Computers, Systems & Signal Processing, pp. 1116?1119, December 1984."},{"key":"CR2","unstructured":"R.E. Bryant, ?Race Detection in MOS Circuits By Ternary Simulation,?VLSI '83-VLSI Design of Digital Systems, Proc. IFIP TC10\/WG\/10.5 Int'l Conf., pp. 85?94, 1983."},{"key":"CR3","doi-asserted-by":"crossref","first-page":"160","DOI":"10.1109\/TC.1984.1676408","volume":"33","author":"R.E. Bryant","year":"1984","unstructured":"R.E. Bryant, ?A Switch-Level Model and Simulator for MOS Digital Systems,?IEEE Trans. on Computers, Vol. C-33, pp. 160?177, February 1984.","journal-title":"IEEE Trans. on Computers"},{"key":"CR4","doi-asserted-by":"crossref","unstructured":"R.E. Bryant, ?Boolean Analysis of MOS Circuits,?IEEE Trans. on Computer-Aided Design of Integrated Circuits, pp. 634?649, July 1987.","DOI":"10.1109\/TCAD.1987.1270310"},{"key":"CR5","doi-asserted-by":"crossref","unstructured":"R.E. Bryant, D. Beatty, K. Brace, K. Cho, and T. Sheffler. ?COSMOS: A Compiled Simulator for MOS Circuits,?Proc. 24th Design Automation Conference, pp. 9?16, June 1987.","DOI":"10.1145\/37888.37890"},{"key":"CR6","doi-asserted-by":"crossref","first-page":"178","DOI":"10.1109\/TC.1979.1675317","volume":"28","author":"J.A. Brzozowski","year":"1979","unstructured":"J.A. Brzozowski and M. Yoeli, ?On a Ternary Model of Gate Networks,?IEEE Trans. on Computers, Vol. C-28, pp. 178?183, March 1979.","journal-title":"IEEE Trans. on Computers"},{"key":"CR7","doi-asserted-by":"crossref","first-page":"359","DOI":"10.1007\/BF00135339","volume":"3","author":"C. Chen","year":"1992","unstructured":"C. Chen and J.A. Abraham, ?Generation and Evaluation of Current and Logic Tests for Switch-Level Sequential Circuits,?Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 3, pp. 359?366, December 1992.","journal-title":"Journal of Electronic Testing: Theory and Applications (JETTA)"},{"key":"CR8","unstructured":"H.H. Chen, R.G. Mathews, and J.A. Newkirk, ?An Algorithm to Generate Tests For MOS Circuits at the Switch Level?Proc. Int'l Test Conference, pp. 304?312, November 1985."},{"key":"CR9","doi-asserted-by":"crossref","unstructured":"K. Cho and R.E. Bryant, ?Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation,?Proc. 26th Design Automation Conference, pp. 418?423, June 1989.","DOI":"10.1145\/74382.74452"},{"key":"CR10","doi-asserted-by":"crossref","unstructured":"K.L. Einspahr and S.C. Seth, ?A Switch-Level Test Generation System?Proc. Fifth International Conference on VLSI Design, pp. 43?48, January 1992.","DOI":"10.1109\/ICVD.1992.658019"},{"key":"CR11","doi-asserted-by":"crossref","first-page":"215","DOI":"10.1109\/TC.1981.1675757","volume":"30","author":"P. Goel","year":"1981","unstructured":"P. Goel, ?An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits,?IEEE Trans. on Computers, Vol. C-30, pp. 215?222, March 1981.","journal-title":"IEEE Trans. on Computers"},{"key":"CR12","doi-asserted-by":"crossref","unstructured":"S.K. Jain and V.D. Agrawal, ?Test Generation for MOS Circuits Using D-Algorithm,?Proc. 20th Design Automation Conference, pp. 64?70, June 1983.","DOI":"10.1109\/DAC.1983.1585627"},{"key":"CR13","doi-asserted-by":"crossref","unstructured":"H.K. Lee and D.S. Ha, ?SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits,?Proc. 27th Design Automation Conf., pp. 660?666, June 1990.","DOI":"10.1145\/123186.123432"},{"key":"CR14","unstructured":"K.J. Lee, ?Switch-Level Test Generation for CMOS Circuits,?Ph.D. Dissertation, Univ. of Southern California, August 1991."},{"key":"CR15","doi-asserted-by":"crossref","unstructured":"A. Lioy, ?Mixed Level Test Generation For MOS Circuits,?Proc. 1st European Test Conference, pp. 208?211, April 1989.","DOI":"10.1109\/ETC.1989.36245"},{"key":"CR16","doi-asserted-by":"crossref","unstructured":"R.A. Marlett, ?An Effective Test Generation System for Sequential Circuits,?Proc. 23rd Design Automation Conference, pp. 250?256 June 1986.","DOI":"10.1109\/DAC.1986.1586097"},{"key":"CR17","unstructured":"M.K. Reddy, ?Testable CMOS Digital Designs and Switch-Level Test Generation for MOS Digital Circuits,?Ph.D. Dissertation, Univ. of Iowa, 1991."},{"key":"CR18","doi-asserted-by":"crossref","unstructured":"M.K. Reddy, S.M. Reddy, and P. Agrawal, ?Transistor Level Test Generation for MOS Circuits,?Proc. 22nd Design Automation Conference, pp. 825?828, June 1985.","DOI":"10.1109\/DAC.1985.1586046"},{"key":"CR19","doi-asserted-by":"crossref","unstructured":"D.G. Saab, T.G. Saab, and J.A. Abraham, ?CRIS: A Test Cultivation Program for Sequential VLSI Circuits,?Proc. Int. Conf. on Computer-Aided Design, pp. 216?217, November 1992.","DOI":"10.1109\/ICCAD.1992.279372"},{"key":"CR20","doi-asserted-by":"crossref","unstructured":"U. Gl\u00e4ser, U. H\u00fcbner and H.T. Vierhaus, ?Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects,?Proc. Int. Test Conf., pp. 21?29, 1992.","DOI":"10.1109\/TEST.1992.528533"},{"key":"CR21","doi-asserted-by":"crossref","first-page":"225","DOI":"10.1007\/BF00971972","volume":"4","author":"Z. Zhang","year":"1993","unstructured":"Z. Zhang, R.D. McLeod, and W. Pedrycz, ?A Neural Network Algorithm for Testing Stuck-Open Faults in CMOS CombinationalCircuits,?Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 4, pp. 225?235, August, 1993.","journal-title":"Journal of Electronic Testing: Theory and Applications (JETTA)"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF00993130.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF00993130\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF00993130","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,22]],"date-time":"2024-12-22T16:13:44Z","timestamp":1734884024000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF00993130"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,2]]},"references-count":21,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1995,2]]}},"alternative-id":["BF00993130"],"URL":"https:\/\/doi.org\/10.1007\/bf00993130","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[1995,2]]}}}