{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,10]],"date-time":"2024-09-10T02:45:36Z","timestamp":1725936336050},"publisher-location":"Singapore","reference-count":15,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811074691"},{"type":"electronic","value":"9789811074707"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-981-10-7470-7_55","type":"book-chapter","created":{"date-parts":[[2017,12,20]],"date-time":"2017-12-20T18:17:13Z","timestamp":1513793833000},"page":"570-577","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A Custom Designed RISC-V ISA Compatible Processor for SoC"],"prefix":"10.1007","author":[{"given":"Kavya","family":"Sharat","sequence":"first","affiliation":[]},{"given":"Sumeet","family":"Bandishte","sequence":"additional","affiliation":[]},{"given":"Kuruvilla","family":"Varghese","sequence":"additional","affiliation":[]},{"given":"Amrutur","family":"Bharadwaj","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2017,12,21]]},"reference":[{"key":"55_CR1","unstructured":"RISC-V, The Free and Open RISC Instruction Set Architecture. RISC-V Foundation (2016). https:\/\/riscv.org . Accessed 14 Jun 2016"},{"key":"55_CR2","unstructured":"Waterman, A., Lee, Y., Patterson, D.A., Asanovic, K.: The RISC-V instruction set manual, volume i: base user-level ISA. EECS Department, UC Berkeley, Technical report UCB\/EECS-2011-62 (2011)"},{"key":"55_CR3","unstructured":"Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach. Elsevier (2011)"},{"key":"55_CR4","unstructured":"Chisel. The Regents of the University of California (2015). https:\/\/chisel.eecs.berkeley.edu . Accessed 14 Jun 2016"},{"key":"55_CR5","volume-title":"Z-Scale: Tiny 32-bit RISC-V Systems with Updates to the Rocket Chip generator","author":"A Magyar","year":"2015","unstructured":"Magyar, A., Lee, Y., Ou, A.: Z-Scale: Tiny 32-bit RISC-V Systems with Updates to the Rocket Chip generator. The International House, Berkeley (2015)"},{"key":"55_CR6","unstructured":"Verilog version of Z-scale, vscale (2016). https:\/\/github.com\/ucb-bar\/vscale . Accessed 14 Jun 2016"},{"key":"55_CR7","unstructured":"Schmidt, C.: \u201cRISC-V\u201d Rocket Chip \u201cTutorial\u201d. UC Berkeley (2015)"},{"key":"55_CR8","doi-asserted-by":"crossref","unstructured":"Duran, L.R.C., et al.: A 32-bit RISC-V AXI4-lite bus-based Microcontroller with 10-bit SAR ADC. In: VII Latin American Symposium on Circuits and Systems (LASCAS) (2016)","DOI":"10.1109\/LASCAS.2016.7451073"},{"key":"55_CR9","unstructured":"PULPino. http:\/\/www.pulp-platform.org . Accessed 25 May 2017"},{"key":"55_CR10","unstructured":"https:\/\/en.wikipedia.org\/wiki\/LowRISC . Accessed 25 May 2017"},{"key":"55_CR11","doi-asserted-by":"crossref","unstructured":"Waterman, A., Lee, Y., et al.: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture. CS Division, EECS Department, University of California, Berkeley (2015)","DOI":"10.21236\/ADA605735"},{"key":"55_CR12","unstructured":"Girard, O.: OpenCores openMSP430, Revision 1.13, 19 May 2015"},{"key":"55_CR13","unstructured":"Error Detection and Correction: Supplement to Logic and Computer Design Fundamentals. Pearson Education (2004)"},{"key":"55_CR14","doi-asserted-by":"crossref","unstructured":"Duran, C., Rueda, L., Castillo, G., et al.: A 32-bit 100 MHz RISC-V Microcontroller with 10-bit SAR ADC in 130 nm CMOS GP. In: Third RISC-V Workshop Proceedings (2016)","DOI":"10.1109\/LASCAS.2016.7451073"},{"key":"55_CR15","doi-asserted-by":"crossref","unstructured":"Gupta, S., Gala, N., et al.: SHAKTI-F: a fault tolerant microprocessor architecture. In: IEEE 24th Asian Test Symposium (2015)","DOI":"10.1109\/ATS.2015.35"}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-10-7470-7_55","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,10]],"date-time":"2022-08-10T23:01:34Z","timestamp":1660172494000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-10-7470-7_55"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9789811074691","9789811074707"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/978-981-10-7470-7_55","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2017]]}}}