{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T16:59:58Z","timestamp":1725641998392},"publisher-location":"Berlin, Heidelberg","reference-count":23,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642272561"},{"type":"electronic","value":"9783642272578"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-27257-8_10","type":"book-chapter","created":{"date-parts":[[2011,12,12]],"date-time":"2011-12-12T00:50:42Z","timestamp":1323651042000},"page":"151-165","source":"Crossref","is-referenced-by-count":4,"title":["Implementation and Evaluation of an SCA-Resistant Embedded Processor"],"prefix":"10.1007","author":[{"given":"Stefan","family":"Tillich","sequence":"first","affiliation":[]},{"given":"Mario","family":"Kirschbaum","sequence":"additional","affiliation":[]},{"given":"Alexander","family":"Szekely","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"10_CR1","doi-asserted-by":"crossref","unstructured":"Ambrose, J.A., Parameswaran, S., Ignjatovic, A.: MUTE-AES: A Multiprocessor Architecture to prevent Power Analysis based Side Channel Attack of the AES Algorithm. In: IEEE\/ACM International Conference on Computer-Aided Design (ICCAD) 2008, pp. 678\u2013684. IEEE (2008)","DOI":"10.1109\/ICCAD.2008.4681650"},{"key":"10_CR2","doi-asserted-by":"crossref","unstructured":"Barthe, L., Benoit, P., Torres, L.: Investigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor Architectures. In: 2010 International Conference on Field Programmable Logic and Applications, pp. 139\u2013144. IEEE Computer Society (2010)","DOI":"10.1109\/FPL.2010.35"},{"key":"10_CR3","unstructured":"Faraday Technology Corporation. Faraday FSA0A_C 0.18 \u03bcm ASIC Standard Cell Library (2004), Details, http:\/\/www.faraday-tech.com"},{"key":"10_CR4","unstructured":"Gaisler Research. GRLIB IP Library User\u2019s Manual. Version 1.1.0 B4100 (October 2010) http:\/\/www.gaisler.com\/products\/grlib\/grlib.pdf"},{"key":"10_CR5","doi-asserted-by":"crossref","unstructured":"Kirschbaum, M., Popp, T.: Evaluation of a DPA-Resistant Prototype Chip. In: 25th Annual Computer Security Applications Conference (ACSAC 2009), Honolulu, Hawaii, USA, December 7-11 (2009)","DOI":"10.1109\/ACSAC.2009.14"},{"key":"10_CR6","unstructured":"Kumar, S.S., Paar, C., Pelzl, J., Pfeiffer, G., Rupp, A., Schimmler, M.: How to Break DES for 8,980. In: Workshop on Special-purpose Hardware for Attacking Cryptographic Systems - SHARCS 2006, Cologne, Germany, April 3-4 (2006)"},{"key":"10_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"101","DOI":"10.1007\/11894063_9","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2006","author":"S. Kumar","year":"2006","unstructured":"Kumar, S., Paar, C., Pelzl, J., Pfeiffer, G., Schimmler, M.: Breaking Ciphers with COPACOBANA \u2013A Cost-Optimized Parallel Code Breaker. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol.\u00a04249, pp. 101\u2013118. Springer, Heidelberg (2006)"},{"key":"10_CR8","volume-title":"Power Analysis Attacks \u2013 Revealing the Secrets of Smart Cards","author":"S. Mangard","year":"2007","unstructured":"Mangard, S., Oswald, E., Popp, T.: Power Analysis Attacks \u2013 Revealing the Secrets of Smart Cards. Springer, Heidelberg (2007) ISBN 978-0-387-30857-9"},{"key":"10_CR9","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"351","DOI":"10.1007\/978-3-540-30574-3_24","volume-title":"Topics in Cryptology \u2013 CT-RSA 2005","author":"S. Mangard","year":"2005","unstructured":"Mangard, S., Popp, T., Gammel, B.M.: Side-Channel Leakage of Masked CMOS Gates. In: Menezes, A. (ed.) CT-RSA 2005. LNCS, vol.\u00a03376, pp. 351\u2013365. Springer, Heidelberg (2005)"},{"key":"10_CR10","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"157","DOI":"10.1007\/11545262_12","volume-title":"Cryptographic Hardware and Embedded Systems \u2013 CHES 2005","author":"S. Mangard","year":"2005","unstructured":"Mangard, S., Pramstaller, N., Oswald, E.: Successfully Attacking Masked AES Hardware Implementations. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol.\u00a03659, pp. 157\u2013171. Springer, Heidelberg (2005)"},{"key":"10_CR11","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"115","DOI":"10.1007\/3-540-47719-5_11","volume-title":"Information Security and Privacy","author":"D. May","year":"2001","unstructured":"May, D., Muller, H.L., Smart, N.P.: Non-deterministic Processors. In: Varadharajan, V., Mu, Y. (eds.) ACISP 2001. LNCS, vol.\u00a02119, pp. 115\u2013129. Springer, Heidelberg (2001)"},{"key":"10_CR12","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"258","DOI":"10.1007\/978-3-642-17955-6_19","volume-title":"Information Security Applications","author":"D. Nakatsu","year":"2011","unstructured":"Nakatsu, D., Li, Y., Sakiyama, K., Ohta, K.: Combination of SW Countermeasure and CPU Modification on FPGA against Power Analysis. In: Chung, Y., Yung, M. (eds.) WISA 2010. LNCS, vol.\u00a06513, pp. 258\u2013272. Springer, Heidelberg (2011)"},{"key":"10_CR13","unstructured":"Alfke, P.: Xilinx Application note on Shift Registers and LFSR counters (July 1996), http:\/\/www.xilinx.com\/support\/documentation\/application_notes\/xapp052.pdf"},{"key":"10_CR14","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"81","DOI":"10.1007\/978-3-540-74735-2_6","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2007","author":"T. Popp","year":"2007","unstructured":"Popp, T., Kirschbaum, M., Zefferer, T., Mangard, S.: Evaluation of the Masked Logic Style MDPL on a Prototype Chip. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol.\u00a04727, pp. 81\u201394. Springer, Heidelberg (2007)"},{"key":"10_CR15","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"172","DOI":"10.1007\/11545262_13","volume-title":"Cryptographic Hardware and Embedded Systems \u2013 CHES 2005","author":"T. Popp","year":"2005","unstructured":"Popp, T., Mangard, S.: Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol.\u00a03659, pp. 172\u2013186. Springer, Heidelberg (2005)"},{"key":"10_CR16","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"205","DOI":"10.1007\/978-3-642-04138-9_15","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2009","author":"F. Regazzoni","year":"2009","unstructured":"Regazzoni, F., Cevrero, A., Standaert, F.-X., Badel, S., Kluter, T., Brisk, P., Leblebici, Y., Ienne, P.: A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. In: Clavier, C., Gaj, K. (eds.) CHES 2009. LNCS, vol.\u00a05747, pp. 205\u2013219. Springer, Heidelberg (2009) ISBN 978-3-642-04137-2"},{"key":"10_CR17","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"95","DOI":"10.1007\/978-3-540-74735-2_7","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2007","author":"P. Schaumont","year":"2007","unstructured":"Schaumont, P., Tiri, K.: Masking and Dual-Rail Logic Don\u2019t Add Up. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol.\u00a04727, pp. 95\u2013106. Springer, Heidelberg (2007)"},{"key":"10_CR18","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"255","DOI":"10.1007\/11894063_21","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2006","author":"D. Suzuki","year":"2006","unstructured":"Suzuki, D., Saeki, M.: Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol.\u00a04249, pp. 255\u2013269. Springer, Heidelberg (2006)"},{"key":"10_CR19","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"303","DOI":"10.1007\/978-3-540-74735-2_21","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2007","author":"S. Tillich","year":"2007","unstructured":"Tillich, S., Gro\u00dfsch\u00e4dl, J.: Power Analysis Resistant AES Implementation with Instruction Set Extensions. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol.\u00a04727, pp. 303\u2013319. Springer, Heidelberg (2007)"},{"key":"10_CR20","doi-asserted-by":"crossref","unstructured":"Tillich, S., Kirschbaum, M., Szekely, A.: SCA-Resistant Embedded Processors\u2014The Next Generation. In: 26th Annual Computer Security Applications Conference (ACSAC 2010), Austin, Texas, USA, December 6-10, pp. 211\u2013220. ACM (2010)","DOI":"10.1145\/1920261.1920293"},{"key":"10_CR21","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"134","DOI":"10.1007\/978-3-540-74462-7_10","volume-title":"Selected Areas in Cryptography","author":"K. Tiri","year":"2007","unstructured":"Tiri, K., Schaumont, P.: Changing the Odds Against Masked Logic. In: Biham, E., Youssef, A.M. (eds.) SAC 2006. LNCS, vol.\u00a04356, pp. 134\u2013146. Springer, Heidelberg (2007), http:\/\/rijndael.ece.vt.edu\/schaum\/papers\/2006sac.pdf"},{"key":"10_CR22","doi-asserted-by":"crossref","unstructured":"Tiri, K., Verbauwhede, I.: A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), Paris, France, February 16-20, vol.\u00a01, pp. 246\u2013251. IEEE Computer Society (2004) ISBN 0-7695-2085-5","DOI":"10.1109\/DATE.2004.1268856"},{"key":"10_CR23","doi-asserted-by":"crossref","unstructured":"Yu, P., Schaumont, P.: Secure FPGA circuits using controlled placement and routing. In: Proceedings of the 5th IEEE\/ACM International Conference on Hardware\/Software Codesign and System Synthesis, Salzburg, Austria, September 30 - October 5, pp. 45\u201350. ACM Press (2007) ISBN 978-1-59593-824-4","DOI":"10.1145\/1289816.1289831"}],"container-title":["Lecture Notes in Computer Science","Smart Card Research and Advanced Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-27257-8_10.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,24]],"date-time":"2020-11-24T02:59:15Z","timestamp":1606186755000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-27257-8_10"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642272561","9783642272578"],"references-count":23,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-27257-8_10","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}