{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T14:01:49Z","timestamp":1725544909552},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642118012"},{"type":"electronic","value":"9783642118029"}],"license":[{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010]]},"DOI":"10.1007\/978-3-642-11802-9_31","type":"book-chapter","created":{"date-parts":[[2010,2,5]],"date-time":"2010-02-05T17:47:19Z","timestamp":1265392039000},"page":"266-275","source":"Crossref","is-referenced-by-count":3,"title":["Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities"],"prefix":"10.1007","author":[{"given":"Bettina","family":"Rebaud","sequence":"first","affiliation":[]},{"given":"Marc","family":"Belleville","sequence":"additional","affiliation":[]},{"given":"Edith","family":"Beign\u00e9","sequence":"additional","affiliation":[]},{"given":"Christian","family":"Bernard","sequence":"additional","affiliation":[]},{"given":"Michel","family":"Robert","sequence":"additional","affiliation":[]},{"given":"Philippe","family":"Maurine","sequence":"additional","affiliation":[]},{"given":"Nadine","family":"Azemard","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"31_CR1","unstructured":"Narayanan, V., et al.: Proc. 18th ACM Great Lakes Symposium on VLSI, Orlando, Florida, USA (2008)"},{"issue":"4","key":"31_CR2","doi-asserted-by":"publisher","first-page":"801","DOI":"10.1109\/TCAD.2006.884860","volume":"26","author":"B. Lasbouygues","year":"2007","unstructured":"Lasbouygues, B., et al.: Temperature- and Voltage-Aware Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems\u00a026(4), 801\u2013815 (2007)","journal-title":"IEEE Trans. on CAD of Integrated Circuits and Systems"},{"key":"31_CR3","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"191","DOI":"10.1007\/978-3-540-74442-9_19","volume-title":"Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation","author":"C.. Parthasarathy","year":"2007","unstructured":"Parthasarathy, C., Bravaix, A., Gu\u00e9rin, C., Denais, M., Huard, V.: Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation. In: Az\u00e9mard, N., Svensson, L. (eds.) PATMOS 2007. LNCS, vol.\u00a04644, pp. 191\u2013200. Springer, Heidelberg (2007)"},{"issue":"6","key":"31_CR4","doi-asserted-by":"publisher","first-page":"438","DOI":"10.1109\/MDT.2006.157","volume":"23","author":"M. Nourani","year":"2006","unstructured":"Nourani, M., Radhakrishnan, A.: Testing On-Die Process Variation in Nanometer VLSI. IEEE Design & Test of Computers\u00a023(6), 438\u2013451 (2006)","journal-title":"IEEE Design & Test of Computers"},{"key":"31_CR5","unstructured":"Samaan, S.B.: Parameter Variation Probing Technique: US Patent 6535013 (2003)"},{"key":"31_CR6","unstructured":"Persun, M.: Method and apparatus for measuring relative, within-die leakage current and\/or providing a temperature variation profile using a leakage inverter and ring oscillators: US Patent 7193427 (2007)"},{"key":"31_CR7","doi-asserted-by":"crossref","unstructured":"Drake, A., et al.: A Distributed Critical Path Timing Monitor for A 65nm High Performance Microprocessor. In: ISSCC, pp. 398\u2013399 (2007)","DOI":"10.1109\/ISSCC.2007.373462"},{"issue":"4","key":"31_CR8","first-page":"792","volume":"41","author":"S. Das","year":"2006","unstructured":"Das, S., et al.: A Self-Tuning DVS Processor Using Delay-Error Detection and Correction. IEEE JSSC\u00a041(4), 792\u2013804 (2006)","journal-title":"IEEE JSSC"},{"key":"31_CR9","doi-asserted-by":"crossref","unstructured":"Blaauw, D., et al.: Razor II: In situ error detection and correction for PVT and SER tolerance. In: ISSCC, pp. 400\u2013401 (2008)","DOI":"10.1109\/ISSCC.2008.4523226"},{"key":"31_CR10","doi-asserted-by":"crossref","unstructured":"Bowman, K.A., et al.: Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance. In: ISSCC, pp. 402\u2013623 (2008)","DOI":"10.1109\/ISSCC.2008.4523227"},{"key":"31_CR11","doi-asserted-by":"crossref","unstructured":"Rebaud, B., et al.: An Innovative Timing Slack Monitor for Variation Tolerant Circuits. In: ICICDT (2009)","DOI":"10.1109\/ICICDT.2009.5166299"},{"key":"31_CR12","doi-asserted-by":"crossref","unstructured":"Agarwal, M., et al.: Circuit Failure Prediction and Its Application to Transistor Aging. In: Proc. VLSI Test Symposium, pp. 277\u2013286 (2007)","DOI":"10.1109\/VTS.2007.22"},{"key":"31_CR13","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"138","DOI":"10.1007\/978-3-540-74442-9_14","volume-title":"Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation","author":"V. Migairou","year":"2007","unstructured":"Migairou, V., Wilson, R., Engels, S., Wu, Z., Azemard, N., Maurine, P.: A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. In: Az\u00e9mard, N., Svensson, L. (eds.) PATMOS 2007. LNCS, vol.\u00a04644, pp. 138\u2013147. Springer, Heidelberg (2007)"},{"issue":"4","key":"31_CR14","doi-asserted-by":"publisher","first-page":"589","DOI":"10.1109\/TCAD.2007.907047","volume":"27","author":"D. Blaauw","year":"2008","unstructured":"Blaauw, D., et al.: Statistical timing analysis: From basic principles to state of the art. IEEE Trans. on CAD of Integrated Circuits and Systems\u00a027(4), 589\u2013607 (2008)","journal-title":"IEEE Trans. on CAD of Integrated Circuits and Systems"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-11802-9_31","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,19]],"date-time":"2019-05-19T17:37:36Z","timestamp":1558287456000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-11802-9_31"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"ISBN":["9783642118012","9783642118029"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-11802-9_31","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2010]]}}}