{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T11:47:03Z","timestamp":1725536823057},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642038686"},{"type":"electronic","value":"9783642038693"}],"license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1007\/978-3-642-03869-3_31","type":"book-chapter","created":{"date-parts":[[2009,8,22]],"date-time":"2009-08-22T00:04:48Z","timestamp":1250899488000},"page":"309-320","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Paired ROBs: A Cost-Effective Reorder Buffer Sharing Strategy for SMT Processors"],"prefix":"10.1007","author":[{"given":"R.","family":"Ubal","sequence":"first","affiliation":[]},{"given":"J.","family":"Sahuquillo","sequence":"additional","affiliation":[]},{"given":"S.","family":"Petit","sequence":"additional","affiliation":[]},{"given":"P.","family":"L\u00f3pez","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"31_CR1","doi-asserted-by":"crossref","unstructured":"Tullsen, D., Eggers, S., Levy, H.: Simultaneous Multithreading: Maximizing On-Chip Parallelism. In: Proc. of the 22nd Annual International Symposium on Computer Architecture (1995)","DOI":"10.1145\/223982.224449"},{"key":"31_CR2","unstructured":"El-Moursy, A., Albonesi, D.H.: Front-End Policies for Improved Issue Efficiency in SMT Processors. In: Proc. of the 9th International Conference on High Performance Computer Architecture (February 2003)"},{"key":"31_CR3","doi-asserted-by":"crossref","unstructured":"Tullsen, D.M., Eggers, S.J., Emer, J.S., Levy, H.M., Lo, J.L., Stamm, R.L.: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. In: Proc. of the 23rd Annual International Symposium on Computer Architecture (May 1996)","DOI":"10.1145\/232973.232993"},{"key":"31_CR4","doi-asserted-by":"crossref","unstructured":"Sharkey, J., Balkan, D., Ponomarev, D.: Adaptive Reorder Buffers for SMT Processors. In: Proc. of the 15 International Conference on Parallel Architectures and Compilation Techniques, pp. 244\u2013253 (2006)","DOI":"10.1145\/1152154.1152192"},{"key":"31_CR5","unstructured":"Cazorla, F.J., Ram\u00edrez, A., Valero, M., Fern\u00e1ndez, E.: Dynamically Controlled Resource Allocation in SMT Processors. In: Proc. of the 37th Annual IEEE\/ACM International Symposium on Microarchitecture (December 2004)"},{"key":"31_CR6","doi-asserted-by":"crossref","unstructured":"Choi, S., Yeung, D.: Learning-Based SMT Processor Resource Distribution via Hill-Climbing. In: Proc. of the 33rd Annual International Symposium on Computer Architecture (June 2006)","DOI":"10.1145\/1150019.1136507"},{"key":"31_CR7","unstructured":"Raasch, S.E., Reinhardt, S.K.: The Impact of Resource Partitioning on SMT Processors. In: Proc. of the 12th International Conference on Parallel Architectures and Compilation Techniques (October 2003)"},{"key":"31_CR8","unstructured":"Sharkey, J., Ponomarev, D.V.: Efficient Instruction Schedulers for SMT Processors. In: Proc. of the 12th International Symposium on High-Performance Computer Architecture (February 2006)"},{"issue":"2","key":"31_CR9","doi-asserted-by":"publisher","first-page":"28","DOI":"10.1109\/40.491460","volume":"16","author":"K.C. Yeager","year":"1996","unstructured":"Yeager, K.C.: The MIPS R10000 Superscalar Microprocessor. IEEE Micro.\u00a016(2), 28\u201341 (1996)","journal-title":"IEEE Micro."},{"key":"31_CR10","doi-asserted-by":"crossref","unstructured":"Ubal, R., Sahuquillo, J., Petit, S., L\u00f3pez, P.: Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors. In: Proc. of the 19th International Symposium on Computer Architecture and High Performance Computing (October 2007), \n \n http:\/\/www.multi2sim.org","DOI":"10.1109\/SBAC-PAD.2007.17"},{"key":"31_CR11","unstructured":"Intel Pentium Processor Extreme Edition (4 threads), \n \n http:\/\/www.intel.com"},{"key":"31_CR12","unstructured":"SPARC Enterprise T5240 (8 threads\/core), \n \n http:\/\/www.fujitsu.com\/sparcenterprise"},{"key":"31_CR13","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"81","DOI":"10.1007\/11573937_11","volume-title":"Advanced Parallel Processing Technologies","author":"C. Liu","year":"2005","unstructured":"Liu, C., Gaudiot, J.L.: Static Partitioning vs Dynamic Sharing of Resources in Simultaneous Multithreading Microarchitectures. In: Cao, J., Nejdl, W., Xu, M. (eds.) APPT 2005. LNCS, vol.\u00a03756, pp. 81\u201390. Springer, Heidelberg (2005)"},{"key":"31_CR14","doi-asserted-by":"crossref","unstructured":"El-Moursy, A., Garg, R., Albonesi, D.H., Dwarkadas, S.: Partitioning Multi-Threaded Processors with a Large Number of Threads. In: Proc. of the IEEE International Symposium on Performance Analysis of Systems and Software (March 2005)","DOI":"10.1109\/ISPASS.2005.1430566"},{"key":"31_CR15","doi-asserted-by":"crossref","unstructured":"Latorre, F., Gonz\u00e1lez, J., Gonz\u00e1lez, A.: Back-end Assignment Schemes for Clustered Multithreaded Processors. In: Proc. of the 18th Annual international Conference on Supercomputing (June 2004)","DOI":"10.1145\/1006209.1006254"},{"key":"31_CR16","unstructured":"Acosta, C., Falcon, A., Ram\u00edrez, A.: A Complexity-Effective Simultaneous Multithreading Architecture. In: Proc. of the 2005 International Conference on Parallel Processing (June 2005)"}],"container-title":["Lecture Notes in Computer Science","Euro-Par 2009 Parallel Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-03869-3_31","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,5,19]],"date-time":"2020-05-19T09:39:21Z","timestamp":1589881161000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-03869-3_31"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"ISBN":["9783642038686","9783642038693"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-03869-3_31","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2009]]},"assertion":[{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}