{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T06:29:06Z","timestamp":1725517746005},"publisher-location":"Berlin, Heidelberg","reference-count":18,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540786092"},{"type":"electronic","value":"9783540786108"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-78610-8_20","type":"book-chapter","created":{"date-parts":[[2008,8,28]],"date-time":"2008-08-28T14:38:28Z","timestamp":1219934308000},"page":"196-208","source":"Crossref","is-referenced-by-count":2,"title":["ARISE Machines: Extending Processors with Hybrid Accelerators"],"prefix":"10.1007","author":[{"given":"Nikolaos","family":"Vassiliadis","sequence":"first","affiliation":[]},{"given":"George","family":"Theodoridis","sequence":"additional","affiliation":[]},{"given":"Spiridon","family":"Nikolaidis","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"20_CR1","doi-asserted-by":"crossref","unstructured":"Hauser, J.R., Wawrzynek, J.: Garp: A MIPS Processor with a Reconfigurable Coprocessor. In: FCCM, pp. 12\u201321 (1997)","DOI":"10.1109\/FPGA.1997.624600"},{"key":"20_CR2","doi-asserted-by":"crossref","unstructured":"Goldstein, S.C., et al.: PipeRench: A Coprocessor for Streaming Multimedia Acceleration. In: ISCA, pp. 28\u201339 (1999)","DOI":"10.1109\/ISCA.1999.765937"},{"key":"20_CR3","doi-asserted-by":"crossref","unstructured":"Singh, H., et al.: MorphoSys: an Integrated Reconfigurable System for Data Parallel and Computation-Intensive Applications. IEEE Trans. on Comp. 465\u2013481 (2000)","DOI":"10.1109\/12.859540"},{"issue":"11","key":"20_CR4","doi-asserted-by":"publisher","first-page":"1363","DOI":"10.1109\/TC.2004.104","volume":"53","author":"S. Vassiliadis","year":"2004","unstructured":"Vassiliadis, S., et al.: The Molen Polymorphic Processor. IEEE Trans. on Comp.\u00a053(11), 1363\u20131375 (2004)","journal-title":"IEEE Trans. on Comp."},{"key":"20_CR5","doi-asserted-by":"crossref","unstructured":"Clark, N., et al.: An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors. In: ISCA, pp. 272\u2013283 (2005)","DOI":"10.1109\/ISCA.2005.9"},{"issue":"6","key":"20_CR6","doi-asserted-by":"publisher","first-page":"421","DOI":"10.1080\/00207210600565127","volume":"93","author":"N. Vassiliadis","year":"2006","unstructured":"Vassiliadis, N., et al.: A RISC architecture extended by an efficient tightly coupled reconfigurable unit. Int. Journal of Electronics\u00a093(6), 421\u2013438 (2006)","journal-title":"Int. Journal of Electronics"},{"issue":"11","key":"20_CR7","doi-asserted-by":"publisher","first-page":"1876","DOI":"10.1109\/JSSC.2003.818292","volume":"38","author":"A. Lodi","year":"2003","unstructured":"Lodi, A., et al.: A VLIW Processor with Reconfigurable Instruction Set for Embedded Applications. IEEE Journal of Solid-State Circuits\u00a038(11), 1876\u20131886 (2003)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"20_CR8","doi-asserted-by":"crossref","unstructured":"Hauck, S., et al.: The Chimaera Reconfigurable Functional Unit. In: FCCM, pp. 87\u201396 (1997)","DOI":"10.1109\/FPGA.1997.624608"},{"key":"20_CR9","unstructured":"The ArchC Website: http:\/\/www.archc.org"},{"key":"20_CR10","unstructured":"Guthausch, M.R., et al.: Mibench: A free, commercially representative embedded benchmark suite. In: IEEE 4th Annual Workshop on Workload Characterization, pp. 3\u201314 (2001)"},{"key":"20_CR11","unstructured":"Scott, J., et al.: Designing the Low- Power MoCORE Architecture. In: Int\u2019l. Symp. on Comp. Arch. Power Driven Microarch. Workshop, pp. 145\u2013150 (1998)"},{"key":"20_CR12","doi-asserted-by":"crossref","unstructured":"Alippi, C., et al.: A DAG Based Design Approach for Reconfigurable VLIW Processors. In: IEEE DATE, pp. 778\u2013779 (1999)","DOI":"10.1145\/307418.307504"},{"key":"20_CR13","unstructured":"Machine-SUIF research compiler, http:\/\/www.eecs.harvard.edu\/hube\/research\/machsuif.html"},{"key":"20_CR14","doi-asserted-by":"crossref","unstructured":"Vassiliadis, N., et al.: The ARISE Reconfigurable Instruction Set Extensions Framework. In: Proc. of IC-SAMOS, pp. 153\u2013160 (2007)","DOI":"10.1109\/ICSAMOS.2007.4285746"},{"key":"20_CR15","doi-asserted-by":"crossref","unstructured":"Gupta, S., et al.: SPARK: A High-Level Synthesis Framework for Applying Parallelizing Compiler Transformations. In: Int. Conf. on VLSI Design, pp. 461\u2013466 (2003)","DOI":"10.1109\/ICVD.2003.1183177"},{"key":"20_CR16","doi-asserted-by":"crossref","unstructured":"Goodwin, D., Petkov, D.: Automatic generation of application specific processors. In: Proc. of CASES, pp. 137\u2013147 (2003)","DOI":"10.1145\/951710.951730"},{"key":"20_CR17","doi-asserted-by":"crossref","unstructured":"Atasu, K., et al.: Automatic application-specific instruction-set extensions under micro-architectural constraints. In: Proc. of DAC, pp. 256\u2013261 (2003)","DOI":"10.1145\/775832.775897"},{"issue":"11","key":"20_CR18","first-page":"2035","volume":"26","author":"F. Sun","year":"2007","unstructured":"Sun, F., et al.: Automatic generation of application specific processors. IEEE TCAD\u00a026(11), 2035\u20132045 (2007)","journal-title":"IEEE TCAD"}],"container-title":["Lecture Notes in Computer Science","Reconfigurable Computing: Architectures, Tools and Applications"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-78610-8_20.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,24]],"date-time":"2020-11-24T02:14:59Z","timestamp":1606184099000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-78610-8_20"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540786092","9783540786108"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-78610-8_20","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[]}}