{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T20:03:43Z","timestamp":1725566623915},"publisher-location":"Berlin, Heidelberg","reference-count":11,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540230953"},{"type":"electronic","value":"9783540302056"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-30205-6_87","type":"book-chapter","created":{"date-parts":[[2010,9,21]],"date-time":"2010-09-21T21:00:42Z","timestamp":1285102842000},"page":"849-858","source":"Crossref","is-referenced-by-count":3,"title":["An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies"],"prefix":"10.1007","author":[{"given":"Peter","family":"Caputa","sequence":"first","affiliation":[]},{"given":"Henrik","family":"Fredriksson","sequence":"additional","affiliation":[]},{"given":"Martin","family":"Hansson","sequence":"additional","affiliation":[]},{"given":"Stefan","family":"Andersson","sequence":"additional","affiliation":[]},{"given":"Atila","family":"Alvandpour","sequence":"additional","affiliation":[]},{"given":"Christer","family":"Svensson","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"87_CR1","doi-asserted-by":"publisher","first-page":"663","DOI":"10.1109\/4.293111","volume":"29","author":"D. Liu","year":"1994","unstructured":"Liu, D., Svensson, C.: Power Consumption Estimation in CMOS VLSI Chips. IEEE J. of Solid-State Circuits\u00a029, 663\u2013670 (1994)","journal-title":"IEEE J. of Solid-State Circuits"},{"key":"87_CR2","doi-asserted-by":"crossref","unstructured":"Chandra, G., Kapur, P., Saraswat, K.C.: Scaling Trends for the On Chip Power Dissipation. In: Proc. of the IEEE 2002 International Interconnect Technology Conference, pp. 154\u2013156 (2002)","DOI":"10.1109\/IITC.2002.1014923"},{"key":"87_CR3","unstructured":"Sotiriadis, P.P.: Interconnect Modeling and Optimization in Deep Sub-Micron Technologies. Ph.D. Thesis, Massachusetts Institute of Technology (May 2002)"},{"key":"87_CR4","doi-asserted-by":"crossref","unstructured":"Macii, E., Poncino, M., Salerno, S.: Combining wire swapping and spacing for lowpower deep-submicron buses. In: Proc. 13th ACM Great Lakes Symposium on VLSI, pp. 198\u2013202 (2003)","DOI":"10.1145\/764808.764859"},{"key":"87_CR5","doi-asserted-by":"crossref","unstructured":"Sakurai, T.: Design challenges for 0.1 \u03bcm and beyond. In: Proc. Asia and South Pacific Design Automation Conf, pp. 293\u2013296 (2001)","DOI":"10.1145\/368434.368787"},{"issue":"3","key":"87_CR6","doi-asserted-by":"publisher","first-page":"341","DOI":"10.1109\/TVLSI.2002.1043337","volume":"10","author":"P.P. Sotiriadis","year":"2002","unstructured":"Sotiriadis, P.P., Chandrakasan, A.P.: A bus energy model for deep submicron technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems\u00a010(3), 341\u2013350 (2002)","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"87_CR7","doi-asserted-by":"publisher","first-page":"397","DOI":"10.1109\/4.375959","volume":"30","author":"M. Hiraki","year":"1995","unstructured":"Hiraki, M., Kojima, H., Misawa, H., Akazawa, T., Hatano, Y.: Data-dependent logic swing internal bus architecture for ultralow-power LSIs. IEEE J. Solid-State Circuits\u00a030, 397\u2013401 (1995)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"87_CR8","doi-asserted-by":"crossref","unstructured":"Kapur, P., Chandra, G., Saraswat, K.C.: Power Estimation in Global Interconnects and its Reduction Using a Novel Repeater Optimization Methodology. In: Proc. 39th Design Automation Conference, pp. 461\u2013466 (2002)","DOI":"10.1145\/513918.514035"},{"key":"87_CR9","doi-asserted-by":"crossref","unstructured":"Sotiriadis, P.P., Konstantakopoulos, T., Chandrakasan, A.P.: Analysis and implementation of charge recycling for deep sub-micron buses. In: International Symposium on Low Power Electronics and Design, August 6-7, pp. 364\u2013369 (2001)","DOI":"10.1145\/383082.383184"},{"issue":"10","key":"87_CR10","doi-asserted-by":"publisher","first-page":"1280","DOI":"10.1109\/TCSI.2003.817765","volume":"50","author":"P.P. Sotiriadis","year":"2003","unstructured":"Sotiriadis, P.P., Chandrakasan, A.P.: Bus energy reduction by transition pattern coding using a detailed deep submicrometer bus model. IEEE Transactions on Circuits and Systems I\u00a050(10), 1280\u20131295 (2003)","journal-title":"IEEE Transactions on Circuits and Systems I"},{"key":"87_CR11","unstructured":"Rabaey, J., Chandrakasan, A.P., Nikolic, B.: Digital Integrated Circuits, a design perspective, 2nd edn. ISBN: 0-13-597444-5"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-30205-6_87.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,5,3]],"date-time":"2021-05-03T03:55:10Z","timestamp":1620014110000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-30205-6_87"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540230953","9783540302056"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-30205-6_87","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2004]]}}}