乐胖代购免代理版

{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,9]],"date-time":"2024-09-09T02:55:16Z","timestamp":1725850516852},"publisher-location":"Cham","reference-count":19,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319298139"},{"type":"electronic","value":"9783319298146"}],"license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016]]},"DOI":"10.1007\/978-3-319-29814-6_15","type":"book-chapter","created":{"date-parts":[[2016,3,7]],"date-time":"2016-03-07T09:04:46Z","timestamp":1457341486000},"page":"184-198","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["QRL: A High Performance Quadruple-Rail Logic for Resisting DPA on FPGA Implementations"],"prefix":"10.1007","author":[{"given":"Chenyang","family":"Tu","sequence":"first","affiliation":[]},{"given":"Jian","family":"Zhou","sequence":"additional","affiliation":[]},{"given":"Neng","family":"Gao","sequence":"additional","affiliation":[]},{"given":"Zeyi","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Yuan","family":"Ma","sequence":"additional","affiliation":[]},{"given":"Zongbin","family":"Liu","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2016,3,5]]},"reference":[{"doi-asserted-by":"crossref","unstructured":"Bhasin, S., Guilley, S., Flament, F., Selmane, N., Danger, J.-L.: Countering early evaluation: an approach towards robust dual-rail precharge logic. In: WESS 2010, p. 6. ACM (2010)","key":"15_CR1","DOI":"10.1145\/1873548.1873554"},{"key":"15_CR2","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"242","DOI":"10.1007\/11894063_20","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2006","author":"Z Chen","year":"2006","unstructured":"Chen, Z., Zhou, Y.: Dual-rail random switching logic: a countermeasure to reduce side channel leakage. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 242\u2013254. Springer, Heidelberg (2006)"},{"doi-asserted-by":"crossref","unstructured":"He, W., de la Torre, E., Riesgo, T.: A precharge-absorbed DPL logic for reducing early propagation effects on FPGA implementations. In: 6th IEEE International Conference on ReConFigurable Computing and FPGAs, Cancun (2011)","key":"15_CR3","DOI":"10.1109\/ReConFig.2011.3"},{"key":"15_CR4","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"39","DOI":"10.1007\/978-3-642-29912-4_4","volume-title":"Constructive Side-Channel Analysis and Secure Design","author":"W He","year":"2012","unstructured":"He, W., de la Torre, E., Riesgo, T.: An interleaved EPE-immune PA-DPL structure for resisting concentrated EM side channel attacks on FPGA implementation. In: Schindler, W., Huss, S.A. (eds.) COSADE 2012. LNCS, vol. 7275, pp. 39\u201353. Springer, Heidelberg (2012)"},{"doi-asserted-by":"crossref","unstructured":"He, W., Otero, A., de la Torre, E., Riesgo, T.: Automatic generation of identical routing pairs for FPGA implemented DPL logic. In: ReConFig 2012, pp. 1\u20136. IEEE (2012)","key":"15_CR5","DOI":"10.1109\/ReConFig.2012.6416733"},{"key":"15_CR6","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"463","DOI":"10.1007\/978-3-540-45146-4_27","volume-title":"Advances in Cryptology - CRYPTO 2003","author":"Y Ishai","year":"2003","unstructured":"Ishai, Y., Sahai, A., Wagner, D.: Private circuits: securing hardware against probing attacks. In: Boneh, D. (ed.) CRYPTO 2003. LNCS, vol. 2729, pp. 463\u2013481. Springer, Heidelberg (2003)"},{"key":"15_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"388","DOI":"10.1007\/3-540-48405-1_25","volume-title":"Advances in Cryptology - CRYPTO \u201999","author":"PC Kocher","year":"1999","unstructured":"Kocher, P.C., Jaffe, J., Jun, B.: Differential power analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388\u2013397. Springer, Heidelberg (1999)"},{"key":"15_CR8","doi-asserted-by":"publisher","first-page":"51","DOI":"10.1049\/iet-ifs.2012.0319","volume":"8","author":"H Marzouqi","year":"2014","unstructured":"Marzouqi, H., Mahmoud, A., Khaled, S.: Review of gate-level differential power analysis and fault analysis countermeasures. Inf. Secur. 8, 51\u201366 (2014). IET","journal-title":"Inf. Secur."},{"doi-asserted-by":"crossref","unstructured":"Nassar, M., Bhasin, S., Danger, J.-L., Duc, G., Guilley, S.: BCDL: a High speed balanced DPL for FPGA with global precharge and no early evaluation. In: Proceedings of Design, Automation and Test in Europe, pp. 849\u2013854. IEEE Computer Society, Dresden (2010)","key":"15_CR9","DOI":"10.1109\/DATE.2010.5456932"},{"key":"15_CR10","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"35","DOI":"10.1007\/978-3-540-45238-6_4","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2003","author":"SB \u00d6rs","year":"2003","unstructured":"\u00d6rs, S.B., Oswald, E., Preneel, B.: Power-analysis attacks on an FPGA \u2013 first experimental results. In: Walter, C.D., Ko\u00e7, \u00c7.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 35\u201350. Springer, Heidelberg (2003)"},{"key":"15_CR11","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"172","DOI":"10.1007\/11545262_13","volume-title":"Cryptographic Hardware and Embedded Systems \u2013 CHES 2005","author":"T Popp","year":"2005","unstructured":"Popp, T., Mangard, S.: Masked dual-rail pre-charge logic: DPA-resistance without routing constraints. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 172\u2013186. Springer, Heidelberg (2005)"},{"doi-asserted-by":"crossref","unstructured":"Soares, R., Calazans, N., Lomne, V., Maurine, P., Torres, L., Robert, M.: Evaluating the robustness of secure triple track logic through prototyping. In: Proceedings of the 21st Symposium on Integrated Circuits and System Design (SBCCI08), Gramado, Brazil, pp. 193\u2013198. ACM, New York (2008)","key":"15_CR12","DOI":"10.1145\/1404371.1404425"},{"key":"15_CR13","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"30","DOI":"10.1007\/978-3-540-28632-5_3","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2004","author":"F-X Standaert","year":"2004","unstructured":"Standaert, F.-X., \u00d6rs, S.B., Preneel, B.: Power analysis of an FPGA implementation of rijndael: is pipelining a DPA countermeasure? In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 30\u201344. Springer, Heidelberg (2004)"},{"key":"15_CR14","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"701","DOI":"10.1007\/978-3-540-45234-8_68","volume-title":"Field Programmable Logic and Application","author":"F-X Standaert","year":"2003","unstructured":"Standaert, F.-X., van Oldeneel tot Oldenzeel, L., Samyde, D., Quisquater, J.-J.: Power analysis of FPGAs: how practical is the attack? In: Cheung, P.Y.K., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 701\u2013711. Springer, Heidelberg (2003)"},{"key":"15_CR15","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"255","DOI":"10.1007\/11894063_21","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2006","author":"D Suzuki","year":"2006","unstructured":"Suzuki, D., Saeki, M.: Security evaluation of DPA countermeasures using dual-rail pre-charge logic style. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 255\u2013269. Springer, Heidelberg (2006)"},{"issue":"3","key":"15_CR16","doi-asserted-by":"publisher","first-page":"57","DOI":"10.1109\/LES.2012.2193115","volume":"4","author":"K Tanimura","year":"2012","unstructured":"Tanimura, K., Dutt, N.: HDRL: homogeneous dual-rail logic for DPA attack resistive secure circuit design. IEEE Embed. Syst. Lett. 4(3), 57\u201360 (2012)","journal-title":"IEEE Embed. Syst. Lett."},{"key":"15_CR17","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"217","DOI":"10.1007\/978-3-319-06320-1_17","volume-title":"Information Security Practice and Experience","author":"C Tu","year":"2014","unstructured":"Tu, C., He, W., Gao, N., de la Torre, E., Liu, Z., Liu, L.: A progressive dual-rail routing repair approach for FPGA implementation of crypto algorithm. In: Huang, X., Zhou, J. (eds.) ISPEC 2014. LNCS, vol. 8434, pp. 217\u2013231. Springer, Heidelberg (2014)"},{"unstructured":"Tiri, K., Verbauwhede, I.: A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation. In: DATE 2004, Vol. 1, pp. 246\u2013251. IEEE Computer Society, Los Alamitos (2004)","key":"15_CR18"},{"doi-asserted-by":"crossref","unstructured":"Yu, P., Schaumont, P.: Secure FPGA circuits using controlled placement and routing. In: Hardware\/Software Codesign and System Synthesis - CODES+ISSS 2007, pp. 45\u201350. ACM, New York (2007)","key":"15_CR19","DOI":"10.1145\/1289816.1289831"}],"container-title":["Lecture Notes in Computer Science","Information and Communications Security"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-29814-6_15","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,16]],"date-time":"2021-06-16T06:14:22Z","timestamp":1623824062000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-319-29814-6_15"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"ISBN":["9783319298139","9783319298146"],"references-count":19,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-29814-6_15","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2016]]},"assertion":[{"value":"5 March 2016","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}