{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T21:02:55Z","timestamp":1725570175527},"publisher-location":"New York, NY","reference-count":45,"publisher":"Springer New York","isbn-type":[{"type":"print","value":"9781441964595"},{"type":"electronic","value":"9781441964601"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-1-4419-6460-1_1","type":"book-chapter","created":{"date-parts":[[2010,11,23]],"date-time":"2010-11-23T22:06:01Z","timestamp":1290549961000},"page":"1-21","source":"Crossref","is-referenced-by-count":7,"title":["An Introduction to Multi-Core System on Chip \u2013 Trends and Challenges"],"prefix":"10.1007","author":[{"given":"Lionel","family":"Torres","sequence":"first","affiliation":[]},{"given":"Pascal","family":"Benoit","sequence":"additional","affiliation":[]},{"given":"Gilles","family":"Sassatelli","sequence":"additional","affiliation":[]},{"given":"Michel","family":"Robert","sequence":"additional","affiliation":[]},{"given":"Fabien","family":"Clermidy","sequence":"additional","affiliation":[]},{"given":"Diego","family":"Puschini","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2010,11,9]]},"reference":[{"key":"1_CR1_1","unstructured":"Ahmed Jerraya and Wayne Wolf. Multiprocessor Systems-on-Chips. Elsevier Inc, 2004."},{"issue":"10","key":"1_CR2_1","first-page":"1701","volume":"27","author":"Wolf Wayne","year":"2008","unstructured":"Wayne Wolf, Ahmed Jerraya, and Grant Martin. Multiprocessor system-on-chip (MPSoC) technology. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 27(10):1701\u20131713, Oct. 2008.","journal-title":"IEEE Transactions on"},{"key":"1_CR3_1","doi-asserted-by":"crossref","first-page":"681","DOI":"10.1145\/996566.996753","volume-title":"The future of multiprocessor systems-on-chips. In DAC \u201904: Proceed- ings of the 41st annual conference on Design automation","author":"Wolf Wayne","year":"2004","unstructured":"Wayne Wolf. The future of multiprocessor systems-on-chips. In DAC \u201904: Proceedings of the 41st annual Design Automation Conference, pages 681\u2013685, New York, NY, USA, 2004. ACM."},{"key":"1_CR4_1","unstructured":"Freescale Semiconductor, Inc. C-5 Network Processor Architecture Guide, 2001. Ref. manual C5NPD0-AG http:\/\/www.freescale.com ."},{"issue":"5","key":"1_CR5_1","doi-asserted-by":"publisher","first-page":"21","DOI":"10.1109\/54.953269","volume":"18","author":"S. Dutta","year":"2001","unstructured":"S. Dutta, R. Jensen, and A. Rieckmann. Viper: A multiprocessor SOC for advanced set-top box and digital TV systems. Design & Test of Computers, IEEE, 18(5):21\u2013 31, Sep-Oct 2001.","journal-title":"Design & Test of Computers, IEEE"},{"key":"1_CR6_1","unstructured":"Texas Instruments Inc. OMAP5912 Multimedia Processor Device Overview and Architecture Reference Guide, 2006. Tech. article SPRU748C. http:\/\/www.ti.com ."},{"issue":"3","key":"1_CR7_1","doi-asserted-by":"publisher","first-page":"412","DOI":"10.1109\/4.826824","volume":"35","author":"B. Ackland","year":"2000","unstructured":"B. Ackland, A. Anesko, D. Brinthaupt, S.J. Daubert, A. Kalavade, J. Knobloch, E. Micca, M. Moturi, C.J. Nicol, J.H. O\u2019Neill, J. Othmer, E. Sackinger, K.J. Singh, J. Sweet, C.J. Terman, and J. Williams. A single-chip, 1.6-billion, 16-b MAC\/s multiprocessor DSP. Solid-State Circuits, IEEE Journal of, 35(3):412\u2013424, Mar 2000.","journal-title":"Solid-State Circuits, IEEE Journal of"},{"key":"1_CR8_1","doi-asserted-by":"crossref","unstructured":"P. Guerrier and A. Greiner. A generic architecture for on-chip packet-switched interconnections. In DATE \u201900: Proceedings of the 2000 Design, Automation and Test in Europe Conference and Exhibition, pages 250\u2013256, 2000.","DOI":"10.1145\/343647.343776"},{"key":"1_CR9_1","doi-asserted-by":"publisher","first-page":"684","DOI":"10.1145\/378239.379048","volume-title":"DAC \u201901: Proceedings of the 38th conference on Design automation","author":"William J. Dally","year":"2001","unstructured":"William J. Dally and Brian Towles. Route packets, not wires: on-chip inteconnection networks. In DAC \u201901: Proceedings of the 38th Design Automation Conference, pages 684\u2013689, New York, NY, USA, 2001. ACM."},{"issue":"1","key":"1_CR10_1","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/2.976921","volume":"35","author":"L. Benini","year":"2002","unstructured":"L. Benini and G. De Micheli. Networks on chips: a new SoC paradigm. IEEE Computer, 35(1):70\u201378, Jan 2002. [cited at p. 3]","journal-title":"IEEE Computer"},{"issue":"1","key":"1_CR11_1","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1132952.1132953","volume":"38","author":"Bjerregaard Tobias","year":"2006","unstructured":"Tobias Bjerregaard and Shankar Mahadevan. A survey of research and practices of Network-on-chip. ACM Comput. Surv., 38(1):1, 2006.","journal-title":"ACM Comput. Surv."},{"issue":"8","key":"1_CR12_1","doi-asserted-by":"publisher","first-page":"1025","DOI":"10.1109\/TC.2005.134","volume":"54","author":"C. Partha Pratim Pande","year":"2005","unstructured":"Partha Pratim Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh. Perfor- mance evaluation and design trade-offs for network-on-chip interconnect architec- tures. Computers, IEEE Transactions on, 54(8):1025\u20131040, Aug. 2005.","journal-title":"IEEE Transactions on"},{"issue":"2","key":"1_CR13_1","doi-asserted-by":"publisher","first-page":"18","DOI":"10.1109\/MCAS.2004.1330747","volume":"4","author":"D. Bertozzi","year":"2004","unstructured":"D. Bertozzi and L. Benini. Xpipes: a network-on-chip architecture for gigas- cale systems-on-chip. Circuits and Systems Magazine, IEEE, 4(2):18\u201331, 2004.","journal-title":"Circuits and Systems Magazine, IEEE"},{"key":"1_CR14_1","doi-asserted-by":"publisher","first-page":"54","DOI":"10.1109\/ASYNC.2005.10","volume-title":"ASYNC \u201905: Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems","author":"E. Beign\u0301e","year":"2005","unstructured":"E. Beign\u0301e, F. Clermidy, P. Vivet, A. Clouard, and M. Renaudin. Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. In ASYNC \u201905: Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems, pages 54\u201363, Washington, DC, USA, 2005. IEEE Computer Society."},{"key":"1_CR15_1","doi-asserted-by":"crossref","unstructured":"J. Pontes, M. Moreira, R. Soares, and N. Calazans. Hermes-glp: A gals network on chip router with power control techniques. In Symposium on VLSI, 2008. ISVLSI \u201908. IEEE Computer Society Annual, pages 347\u2013352, April 2008.","DOI":"10.1109\/ISVLSI.2008.90"},{"key":"1_CR16_1","doi-asserted-by":"publisher","first-page":"110","DOI":"10.1145\/1278480.1278509","volume-title":"DAC \u201907: Pro- ceedings of the 44th Annual Conference on Design Automation","author":"Umit Y. Ogras","year":"2007","unstructured":"Umit Y. Ogras, Radu Marculescu, Puru Choudhary, and Diana Marculescu.Voltage- frequency island partitioning for GALS-based Networks-on-Chip. In DAC \u201907: Proceedings of the 44th Annual Design Automation Conference, pages 110\u2013115, New York, NY, USA, 2007. ACM."},{"key":"1_CR17_1","unstructured":"James Donald and Margaret Martonosi. Techniques for multicore thermal man- agement: Classification and new exploration. In ISCA \u201906: Proceeding of the 33rd International Symposium on Computer Architecture, pages 78\u201388, 2006."},{"key":"1_CR18_1","doi-asserted-by":"crossref","unstructured":"Edith Beign\u0301e, Fabien Clermidy, Sylvain Miermont, and Pascal Vivet. Dynamic voltage and frequency scaling architecture for units integration within a gals noc. In NOCS, pages 129\u2013138, 2008.","DOI":"10.1109\/NOCS.2008.4492732"},{"key":"1_CR19_1","doi-asserted-by":"crossref","unstructured":"Edith Beign\u0301e, Fabien Clermidy, Sylvain Miermont, Alexandre Valentian, Pascal Vivet, S Barasinski, F Blisson, N Kohli, and S Kumar. A fully integrated power supply unit for fine grain dvfs and leakage control validated on low-voltage srams. In ESSCIRC\u201908: Proceeding of the 34th European Solid-State Circuits Conference, Edinburg, UK, Sept. 2008.","DOI":"10.1109\/ESSCIRC.2008.4681811"},{"issue":"8","key":"1_CR20_1","first-page":"114","volume":"38","author":"G. E. Moore","year":"1965","unstructured":"G. E. Moore. Cramming More Components onto Integrated Circuits. Electronics, 38(8):114\u2013117, April 1965.","journal-title":"Electronics"},{"key":"1_CR21_1","unstructured":"The International Technology Roadmap for Semiconductors. International Technology Roadmap for Semiconductors 2008 Update Overview. http:\/\/www.itrs.net ."},{"key":"1_CR22_1","doi-asserted-by":"crossref","unstructured":"Davide Rossi, Fabio Campi, Antonello Deledda, Simone Spolzino and Stefano Pucillo, A Heterogeneous Digital Signal Processor Implementation for Dynamically Reconfigurable Computing, IEEE Custom Integrated Circuits Conference (CICC) September 13 - 16 2009,","DOI":"10.1109\/CICC.2009.5280747"},{"key":"1_CR23_1","doi-asserted-by":"publisher","first-page":"948","DOI":"10.1109\/TC.1972.5009071","volume":"21","author":"M. Flynn","year":"1972","unstructured":"M. Flynn. Some Computer Organizations and Their Effectiveness, IEEE Trans. Computer, vol. 21, pp. 948, 1972","journal-title":"IEEE Trans. Computer"},{"key":"1_CR24_1","unstructured":"A. W. Burks, H. Goldstine, and J. von Neumann. Preliminary Discussion of the Logical Design of an Electronic Computing Instrument, Inst. Advanced Study Rept., vol. 1, June, 1946"},{"key":"1_CR25_1","doi-asserted-by":"crossref","first-page":"93","DOI":"10.1109\/ISVLSI.2008.34","volume-title":"ISVLSI \u201908: Pro- ceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI","author":"Maalej Issam","year":"2008","unstructured":"Issam Maalej, Guy Gogniat, Jean Luc Philippe, and Mohamed Abid. System Level Design Space Exploration for Multiprocessor System on Chip. In ISVLSI \u201908: Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI, pages 93\u201398, Washington, DC, USA, 2008. IEEE Computer Society."},{"key":"1_CR26_1","first-page":"50","volume-title":"SBCCI \u201905: Pro- ceedings of the 18th annual symposium on Integrated circuits and system design","author":"Knerr Bastian","year":"2005","unstructured":"Bastian Knerr, Martin Holzer, and Markus Rupp. Task Scheduling for Power Opti- misation of Multi Frequency synchronous Data Flow Graphs. In SBCCI \u201905: Proceedings of the 18th annual symposium on Integrated circuits and system design, pages 50\u201355, New York, NY, USA, 2005. ACM."},{"issue":"1","key":"1_CR27_1","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1109\/TC.1987.5009446","volume":"36","author":"Edward Ashford Lee","year":"1987","unstructured":"Edward Ashford Lee and David G. Messerschmitt. Static scheduling of synchronous data flow programs for digital signal processing. IEEE Trans. Comput., 36(1):24\u201335, 1987.","journal-title":"IEEE Trans. Comput."},{"key":"1_CR28_1","doi-asserted-by":"crossref","unstructured":"Philippe Grosse, Yves Durand, Paul Feautrier: Methods for power optimization in SOC-based data flow systems. ACM Trans. Design Autom. Electr. Syst. 14(3): (2009)","DOI":"10.1145\/1529255.1529260"},{"issue":"1","key":"1_CR29_1","doi-asserted-by":"publisher","first-page":"56","DOI":"10.1166\/jolpe.2006.007","volume":"2","author":"A. K. Coskun","year":"2006","unstructured":"A. K. Coskun, T. Simunic Rosing, K. Mihic, G. De Micheli, and Y. Leblebici. Analysis and Optimization of MPSoC Reliability. Journal of Low Power Electronics, 2(1):56\u201369, 2006.","journal-title":"Journal of Low Power Electronics"},{"key":"1_CR30_1","first-page":"292","volume-title":"ASP-DAC \u201905: Proceedings of the 2005 Conference on Asia South Pacific Design Automation","author":"Niyogi Koushik","year":"2005","unstructured":"Koushik Niyogi and Diana Marculescu. Speed and voltage selection for GALS sys- tems based on voltage\/frequency islands. In ASP-DAC \u201905: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, pages 292\u2013297, New York, NY, USA, 2005. ACM."},{"key":"1_CR31_1","doi-asserted-by":"crossref","unstructured":"Zeynep Toprak Deniz, Yusuf Leblebici, and Eric Vittoz. Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation. In IFIP 2006: International Conference on Very Large Scale Integration, pages 379\u2013384, Oct. 2006.","DOI":"10.1109\/VLSISOC.2006.313265"},{"key":"1_CR32_1","doi-asserted-by":"crossref","unstructured":"Zeynep Toprak Deniz, Yusuf Leblebici, and Eric Vittoz. On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation. In ESSCIRC 2006: Proceedings of the 32nd European Solid-State Circuits Conference, pages 219\u2013222, Sept. 2006.","DOI":"10.1109\/ESSCIR.2006.307570"},{"key":"1_CR33_1","doi-asserted-by":"publisher","first-page":"111","DOI":"10.1145\/1289816.1289845","volume-title":"CODES+ISSS \u201907: Proceedings of the 5th IEEE\/ACM International Conference on Hardware\/Software Codesign and System Synthesis","author":"Srinivasan Murali","year":"2007","unstructured":"Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen Boyd, and Giovanni De Micheli. Temperature-aware processor frequency assignment for MPSoCs using convex optimization. In CODES+ISSS \u201907: Proceedings of the 5th IEEE\/ACM International Conference on Hardware\/Software Codesign and System Synthesis, pages 111\u2013116, New York, NY, USA, 2007. ACM."},{"key":"1_CR34_1","doi-asserted-by":"publisher","first-page":"110","DOI":"10.1109\/DATE.2008.4484671","volume-title":"DATE\u201908: Design, Automa- tion and Test in Europe","author":"Srinivasan Murali","year":"2008","unstructured":"Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen Boyd, Luca Benini, and Giovanni De Micheli. Temperature control of high-performance multi-core platforms using convex optimization. In DATE\u201908: Design, Automation and Test in Europe, pages 110\u2013115, Munich, Germany, 2008. IEEE Computer Society."},{"key":"1_CR35_1","first-page":"28","volume-title":"RTCSA \u201907: Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Sys- tems and Applications","author":"Chenand Jian-Jia","year":"2007","unstructured":"Jian-Jia Chenand Chin-Fu Kuo. Energy-Efficient Schedulingfor Real-Time Systems on Dynamic Voltage Scaling (DVS) Platforms. In RTCSA \u201907: Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, pages 28\u201338, Washington, DC, USA, 2007. IEEE Computer Society."},{"key":"1_CR36_1","doi-asserted-by":"publisher","first-page":"34","DOI":"10.1109\/RSP.2007.26","volume-title":"RSP \u201907: Proceedings of the 18th IEEE\/IFIP International Workshop on Rapid System Prototyping","author":"Ewerson Carvalho","year":"2007","unstructured":"Ewerson Carvalho, Ney Calazans, and Fernando Moraes. Heuristics for dynamic task mapping in noc-based heterogeneous MPSoCs. In RSP \u201907: Proceedings of the 18th IEEE\/IFIP International Workshop on Rapid System Prototyping, pages 34\u201340, Washington, DC, USA, 2007. IEEE Computer Society."},{"key":"1_CR37_1","first-page":"648","volume-title":"DATE \u201905: Proceedings of the 2005 Conference on Design, Automation and Test in Europe","author":"G. M. Link","year":"2005","unstructured":"G. M. Link and N. Vijaykrishnan. Hotspot prevention through runtime reconfiguration in Network-on-Chip. In DATE \u201905: Proceedings of the 2005 Conference on Design, Automation and Test in Europe, pages 648\u2013649, Washington, DC, USA, 2005. IEEE Computer Society."},{"key":"1_CR38_1","first-page":"1659","volume-title":"DATE \u201907: Proceedings of the conference on Design, automation and test in Europe","author":"Ayse Kivilcim","year":"2007","unstructured":"Ayse Kivilcim Coskun, Tajana Simunic Rosing, and Keith Whisnant. Temperature aware task scheduling in MPSoCs. In DATE \u201907: Proceedings of the conference on Design, automation and test in Europe, pages 1659\u20131664, San Jose, CA, USA, 2007. EDA Consortium."},{"key":"1_CR39_1","first-page":"49","volume-title":"ASP-DAC \u201908: Proceedings of the 2008 conference on Asia and South Pacific design automation","author":"Ayse Kivilcim","year":"2008","unstructured":"Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith A. Whisnant, and Kenny C. Gross. Temperature-aware mpsoc scheduling for reducing hot spots and gradients. In ASP-DAC \u201908: Proceedings of the 2008 conference on Asia and South Pacific design automation, pages 49\u201354, Los Alamitos, CA, USA, 2008. IEEE Computer Society Press."},{"key":"1_CR40_1","doi-asserted-by":"publisher","first-page":"66","DOI":"10.1109\/ISSOC.2005.1595646","volume-title":"SOC\u201905: Proceedings of the International Symposium on System-on-Chip","author":"Ch Ykman-Couvreur","year":"2005","unstructured":"Ch. Ykman-Couvreur, E. Brockmeyer, V. Nollet, Th. Marescaux, Fr. Catthoor, and H. Corporaal. Design-Time Application Exploration for MP-SoC Customized Run- Time Management. In SOC\u201905: Proceedings of the International Symposium on System-on-Chip, pages 66\u201373, Tampere, Finland, November 2005."},{"key":"1_CR41_1","doi-asserted-by":"crossref","unstructured":"Ch. Ykman-Couvreur, V. Nollet, Fr. Catthoor, and H. Corporaal. Fast Multi-Dimension Multi-Choice Knapsack Heuristic for MP-SoC Run-Time Management. In SOC\u201906: Proceedings of the International Symposium on System-on-Chip, pages 195\u2013198, Tampere, Finland, November 2006.","DOI":"10.1109\/ISSOC.2006.321966"},{"key":"1_CR42_1","doi-asserted-by":"crossref","unstructured":"Ch. Ykman-Couvreur, V. Nollet, Th. Marescaux, E. Brockmeyer, Fr. Catthoor, and H. Corporaal. Pareto-based application specification for MP-SoC Customized Run-Time Management. In SAMOS\u201906: Proceedings of the International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation, pages 78\u201384, Samos, Greece, July 2006.","DOI":"10.1109\/ICSAMOS.2006.300812"},{"key":"1_CR43_1","doi-asserted-by":"crossref","unstructured":"D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli, and L. Torres. Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory, Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual, 2008, pp. 375-380.","DOI":"10.1109\/ISVLSI.2008.33"},{"key":"1_CR44_1","doi-asserted-by":"publisher","first-page":"11","DOI":"10.1155\/2008\/403086","volume":"2008","author":"D. Puschini","year":"2008","unstructured":"D. Puschini, F. Clermidy, P. Benoit, and G. Sassatelli. A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC, International Journal of Reconfigurable Computing, vol. 2008, 2008, p. 11.","journal-title":"International Journal of Reconfigurable Computing"},{"key":"1_CR45_1","doi-asserted-by":"crossref","unstructured":"D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli, and L. Torres. Adaptive energy-aware latency-constrained DVFS policy for MPSoC, 2009 IEEE International SOC Conference (SOCC), IEEE, 2009, pp. 89\u201392.","DOI":"10.1109\/SOCCON.2009.5398087"}],"container-title":["Multiprocessor System-on-Chip"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-1-4419-6460-1_1.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,14]],"date-time":"2021-11-14T01:13:18Z","timestamp":1636852398000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-1-4419-6460-1_1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,11,9]]},"ISBN":["9781441964595","9781441964601"],"references-count":45,"URL":"https:\/\/doi.org\/10.1007\/978-1-4419-6460-1_1","relation":{},"subject":[],"published":{"date-parts":[[2010,11,9]]}}}