{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T22:57:27Z","timestamp":1725490647184},"publisher-location":"Berlin, Heidelberg","reference-count":22,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540411284"},{"type":"electronic","value":"9783540399995"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-39999-2_7","type":"book-chapter","created":{"date-parts":[[2007,9,3]],"date-time":"2007-09-03T00:22:39Z","timestamp":1188778959000},"page":"59-72","source":"Crossref","is-referenced-by-count":0,"title":["The Case for Speculative Multithreading on SMT Processors"],"prefix":"10.1007","author":[{"given":"Haitham","family":"Akkary","sequence":"first","affiliation":[]},{"given":"S\u00e9bastien","family":"Hily","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2001,4,6]]},"reference":[{"key":"7_CR1","doi-asserted-by":"crossref","unstructured":"D. M. Tullsen, S. J. Eggers and H. M. Levy. Simultaneous Multithreading: Maximizing on-Chip Parallelism. The 22nd International Symposium on Computer Architecture, June 1995.","DOI":"10.1145\/223982.224449"},{"key":"7_CR2","doi-asserted-by":"crossref","unstructured":"H. Akkary and M.A. Driscoll. A Dynamic Multithreading Processor. The 31st International Symposium on Microarchitecture, November 1998.","DOI":"10.1109\/MICRO.1998.742784"},{"key":"7_CR3","doi-asserted-by":"crossref","unstructured":"D. M. Tullsen, S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo and R. L. Stamm. Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. The 23rd International Symposium on Computer Architecture, May 1996.","DOI":"10.1145\/232973.232993"},{"key":"7_CR4","unstructured":"M. Franklin. The Multiscalar Architecture. Ph.D. Thesis, University of Wisconsin-Madison, November 93."},{"key":"7_CR5","doi-asserted-by":"crossref","unstructured":"G. S. Sohi, S. E. Breach, and T.N. Vijaykumar. Multiscalar Processors. The 22nd International Symposium on Computer Architecture, June 1995.","DOI":"10.1145\/223982.224451"},{"key":"7_CR6","unstructured":"J. Y. Tsai, Z. Jiang, E. Ness, and P.-C. Yew. Performance Study of a Concurrent Multithreaded Processor. The 4th International Symposium on High-Performance Computer Architecture, January 1998."},{"key":"7_CR7","doi-asserted-by":"crossref","unstructured":"J. G. Steffan and T. C. Mowry. The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization. The 4th International Symposium on High-Performance Computer Architecture, January 1998.","DOI":"10.1109\/HPCA.1998.650541"},{"key":"7_CR8","doi-asserted-by":"crossref","unstructured":"S. Wallace, B. Calder, and D. M. Tullsen. Threaded Multiple Path Execution. The 25th International Symposium on Computer Architecture, June 1998.","DOI":"10.1109\/ISCA.1998.694778"},{"key":"7_CR9","doi-asserted-by":"crossref","unstructured":"P. Marcuello, A. Gonz\u00e1lez, and J. Tubella. Speculative Multithreaded Processors. International Conference on Supercomputing\u201998, July 1998.","DOI":"10.1145\/277830.277850"},{"key":"7_CR10","doi-asserted-by":"crossref","unstructured":"V. Krishnan and J. Torrellas. Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-Multiprocessor. International Conference on Snupercomputing\u201998, July 1998.","DOI":"10.1145\/277830.277852"},{"key":"7_CR11","doi-asserted-by":"crossref","unstructured":"L. Hammond, M. Willey, and K. Olukotun. Data Speculation support for a chip multiprocessor. International Conference on Architectural Support for Programming Languages and Operating Systems, October 1998.","DOI":"10.21236\/ADA419653"},{"key":"7_CR12","unstructured":"M. Tremblay. Magic: Microprocessor Architecture for Java Computing. Presentation at HotChips\u201999, August 1999."},{"key":"7_CR13","unstructured":"L. Codrescu and D. S. Wills. Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. The 1999 International Conference on Computer Design, VLSI in Computers & Processors (ICCD\u201999), October 1999."},{"key":"7_CR14","unstructured":"H. Akkary. A Dynamic Multithreading Processor. Ph.D. Thesis, Portland State University, June 1998."},{"issue":"3","key":"7_CR15","doi-asserted-by":"publisher","first-page":"13","DOI":"10.1145\/268806.268810","volume":"25","author":"D. Burger","year":"1997","unstructured":"D. Burger and T. M. Austin. The SimpleScalar Tool Set, Version 2.0. Computer Architecture News, Vol. 25, No. 3, pp. 13\u201325, June 1997.","journal-title":"Computer Architecture News"},{"key":"7_CR16","doi-asserted-by":"crossref","unstructured":"D. Lee, P. Crowley, J.-L. Baer, T. Anderson and B. Bershad. Execution Characteristics of Desktop Applications on Windows NT. The 25th International Symposium on Computer Architecture, June 1998.","DOI":"10.1109\/ISCA.1998.694760"},{"key":"7_CR17","doi-asserted-by":"crossref","unstructured":"A.S. Palacharla, N.P. Jouppi, and J.E. Smith. Complexity-Effective Superscalar Processors. The 24th International Symposium on Computer Architecture, June 1997.","DOI":"10.1145\/264107.264201"},{"key":"7_CR18","doi-asserted-by":"crossref","unstructured":"A. Seznec, S. Jourdan, P. Sainrat, and P. Michaud. Multiple-Block Ahead Branch Predictors. International Conference on Architectural Support for Programming Languages and Operating Systems, October 1996.","DOI":"10.1145\/237090.237169"},{"key":"7_CR19","unstructured":"S. Hily and A. Seznec. Standard Memory Hierarchy Does Not Fit Simultaneous Multithreading. In Proceedings of Workshop on MultiThreaded Execution, Architecture and Compilation, held in conjunction with HPCA-4, Colorado State Univ. Technical Report CS-98\u2013102, January 1998."},{"key":"7_CR20","unstructured":"S.E. Raasch and S.K. Reinhardt. Applications of Thread Prioritization in SMT Processors. In Proceedings of Workshop on MultiThreaded Execution, Architecture and Compilation, held in conjunction with HPCA-5, January 1999."},{"key":"7_CR21","unstructured":"S. Patel, D. Friendly, and Y. Patt. Critical Issues Regarding the Trace Cache Fetch Mechanism. University of Michigan Technical Report CSE-TR-335-97, 1997."},{"key":"7_CR22","unstructured":"E. Rotenberg, S. Bennett, and J. E. Smith. Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching. The 29th International Symposium on Microarchitecture, December 1997."}],"container-title":["Lecture Notes in Computer Science","High Performance Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-39999-2_7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,2]],"date-time":"2019-05-02T19:40:49Z","timestamp":1556826049000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-39999-2_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540411284","9783540399995"],"references-count":22,"URL":"https:\/\/doi.org\/10.1007\/3-540-39999-2_7","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2000]]}}}