{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T15:38:40Z","timestamp":1725550720105},"publisher-location":"Berlin, Heidelberg","reference-count":9,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540296430"},{"type":"electronic","value":"9783540321088"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11572961_50","type":"book-chapter","created":{"date-parts":[[2005,10,18]],"date-time":"2005-10-18T11:06:07Z","timestamp":1129633567000},"page":"614-624","source":"Crossref","is-referenced-by-count":0,"title":["A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture"],"prefix":"10.1007","author":[{"given":"Jin-Ho","family":"Ahn","sequence":"first","affiliation":[]},{"given":"Byung In","family":"Moon","sequence":"additional","affiliation":[]},{"given":"Sungho","family":"Kang","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"50_CR1","doi-asserted-by":"crossref","unstructured":"Benini, L., Micheli, G.D.: Networks on Chips: A New SoC Paradigm. IEEE Computer, 70\u201378 (2002)","DOI":"10.1109\/2.976921"},{"key":"50_CR2","doi-asserted-by":"crossref","unstructured":"Guerrier, P., Greiner, A.: A Generic Architecture for On-Chip Packet-Switched Interconnections. In: Proc. of IEEE DATE, pp. 250\u2013256 (2000)","DOI":"10.1145\/343647.343776"},{"key":"50_CR3","doi-asserted-by":"crossref","unstructured":"Vermeulen, B., Dielissen, J., Goossen, K., Ciordas, C.: Bringing Communication Networks on a Chip: Test and Verification Implications. IEEE Communications Magazine, 74\u201381 (2003)","DOI":"10.1109\/MCOM.2003.1232240"},{"key":"50_CR4","doi-asserted-by":"crossref","unstructured":"Nahvi, M., Ivanov, A.: Indirect Test Architecture for SoC Testing. IEEE Trans. on CAD, 1128\u20131142 (2004)","DOI":"10.1109\/TCAD.2004.829796"},{"key":"50_CR5","unstructured":"Liu, C., Cota, E., Sharif, H., Pradhan, D.K.: Test Scheduling for Network-on-Chip with BIST and Precedence Constraints. Proc. of IEEE ITC, 1369\u20131378 (2004)"},{"key":"50_CR6","doi-asserted-by":"crossref","unstructured":"Cota, E., et al.: The Impact of NoC Reuse on the Testing of Core-based Systems. Proc. of IEEE VTS, 128\u2013133 (2003)","DOI":"10.1109\/VTEST.2003.1197643"},{"key":"50_CR7","doi-asserted-by":"crossref","unstructured":"Cota, E., Carro, L., Wagner, F., Lubaszewski, M.: Power-Aware NoC Reuse on the Testing of Core-Based Systems. Proc. of IEEE ITC, 612\u2013621 (2003)","DOI":"10.1109\/TEST.2003.1270888"},{"key":"50_CR8","doi-asserted-by":"crossref","unstructured":"Amory, A.M., et al.: Reducing Test Time with Processor Reuse in Network-on-Chip Based System. In: Proc. of the 17th Symposium on Integrated Circuits and Systems Design, pp. 111\u2013116 (2004)","DOI":"10.1145\/1016568.1016602"},{"key":"50_CR9","doi-asserted-by":"crossref","unstructured":"Busch, C., Herlihy, M., Wattenhofer, R.: Routing without Flow Control. In: Proc. of the 13th ACM Symposium on Parallel Algorithms and Architectures, pp. 11\u201320 (2001)","DOI":"10.1145\/378580.378582"}],"container-title":["Lecture Notes in Computer Science","Advances in Computer Systems Architecture"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11572961_50.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T19:55:49Z","timestamp":1605642949000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11572961_50"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540296430","9783540321088"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/11572961_50","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2005]]}}}