{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,18]],"date-time":"2025-01-18T20:10:16Z","timestamp":1737231016187,"version":"3.33.0"},"reference-count":9,"publisher":"Wiley","issue":"9","license":[{"start":{"date-parts":[[2007,9,5]],"date-time":"2007-09-05T00:00:00Z","timestamp":1188950400000},"content-version":"vor","delay-in-days":5360,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems & Computers in Japan"],"published-print":{"date-parts":[[1993,1]]},"abstract":"Abstract<\/jats:title>This paper presents a test generation method using an optimization technique for a single stuck\u2010at fault in synchronous sequential circuits. This method utilizes a new real number simulation for defining the cost of an input pattern for a given fault and leads an input pattern to a test pattern by changing the input repeatedly to minimize its cost.<\/jats:p>Since a sequential circuit has internal states, a test pattern for a fault is a sequence of input vectors for several time frames. For generating the whole test pattern, the concept of forward test generation, which performs the convergence calculation process at multiple time frames, is introduced to avoid the problem of local optimum.<\/jats:p>Experimental results for ISCAS '89 benchmark sequential circuits show the effectiveness of the proposed method for sequential circuit test generation.<\/jats:p>","DOI":"10.1002\/scj.4690240907","type":"journal-article","created":{"date-parts":[[2007,7,8]],"date-time":"2007-07-08T01:33:17Z","timestamp":1183858397000},"page":"64-75","source":"Crossref","is-referenced-by-count":0,"title":["Sequential circuit test generation by real number simulation"],"prefix":"10.1002","volume":"24","author":[{"given":"Kazunori","family":"Hikone","sequence":"first","affiliation":[]},{"given":"Mitsuji","family":"Ikeda","sequence":"additional","affiliation":[]},{"given":"Kazumi","family":"Hatayama","sequence":"additional","affiliation":[]},{"given":"Terumine","family":"Hayashi","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2007,9,5]]},"reference":[{"key":"e_1_2_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1967.264743"},{"key":"e_1_2_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675757"},{"key":"e_1_2_1_4_2","doi-asserted-by":"crossref","unstructured":"K. T.ChengandV. D.AgrawalA Sequential Circuit Test Generator Using Threshold\u2010Value Simulation. Digest of Papers 18th Int. Symp. Fault\u2010Tolerant Computing pp.24\u201329(June1988).","DOI":"10.1109\/FTCS.1988.5292"},{"key":"e_1_2_1_5_2","doi-asserted-by":"crossref","unstructured":"V. D.Agrawal K. T.ChengandP.Agrawal.CONTEST: Concurrent Test Generator for Sequential Circuits. Proc. 25th DAC pp.84\u201389(June1988).","DOI":"10.1109\/DAC.1988.14739"},{"key":"e_1_2_1_6_2","article-title":"A Backtrackless Test Generation Method for Combinational Circuits. Papers of Technical Group on Fault Tolerant Systems","volume":"89","author":"Ikeda M.","year":"1989","journal-title":"I.E.I.C.E., Japan"},{"key":"e_1_2_1_7_2","doi-asserted-by":"crossref","unstructured":"F.Brglez D.BryanandK.Kozminski.Combinational Profiles of Sequential Benchmark Circuits. Proc. IEEE Int. Symp. Circuit and System pp.1929\u20131934(May1989).","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"e_1_2_1_8_2","doi-asserted-by":"crossref","unstructured":"A.Lioy P. L.MontessoroandS.Gai.A Complexity Analysis of Sequential ATPG. Proc. IEEE Int. Symp. Circuit and System pp.1946\u20131949(May1989).","DOI":"10.1109\/ISCAS.1989.100751"},{"key":"e_1_2_1_9_2","doi-asserted-by":"crossref","unstructured":"W.\u2010T.ChengandS.Davidson.Sequential Circuit Test Generator (STG) Benchmark Result. Proc. IEEE Int. Symp. Circuit and System pp.1939\u20131941(May1989).","DOI":"10.1109\/ISCAS.1989.100749"},{"key":"e_1_2_1_10_2","article-title":"A forward test generation algorithm for sequential circuits: FORTE. Papers of Technical Group on Fault Tolerant Systems","volume":"91","author":"Takamatsu Y.","year":"1991","journal-title":"I.E.I.C.E., Japan"}],"container-title":["Systems and Computers in Japan"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fscj.4690240907","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/scj.4690240907","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,18]],"date-time":"2025-01-18T19:35:13Z","timestamp":1737228913000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/scj.4690240907"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,1]]},"references-count":9,"journal-issue":{"issue":"9","published-print":{"date-parts":[[1993,1]]}},"alternative-id":["10.1002\/scj.4690240907"],"URL":"https:\/\/doi.org\/10.1002\/scj.4690240907","archive":["Portico"],"relation":{},"ISSN":["0882-1666","1520-684X"],"issn-type":[{"type":"print","value":"0882-1666"},{"type":"electronic","value":"1520-684X"}],"subject":[],"published":{"date-parts":[[1993,1]]}}}