{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,11,14]],"date-time":"2023-11-14T23:10:11Z","timestamp":1700003411458},"reference-count":10,"publisher":"Wiley","issue":"8","license":[{"start":{"date-parts":[[2007,12,19]],"date-time":"2007-12-19T00:00:00Z","timestamp":1198022400000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Circuit Theory & Apps"],"published-print":{"date-parts":[[2008,11]]},"abstract":"Abstract<\/jats:title>In this letter, the voltage imbalance between the dual output DC voltages of a half\u2010bridge boost rectifier with mismatched loads is analyzed by adopting an averaged circuit model. A compensating signal proportional to the voltage difference is added in the current command to eliminate the voltage imbalance. In addition, the adverse effects of the compensating current to the input power factor are discussed. Experimental results on a prototype circuit are given to confirm the theoretical analysis. Copyright \u00a9 2007 John Wiley & Sons, Ltd.<\/jats:p>","DOI":"10.1002\/cta.471","type":"journal-article","created":{"date-parts":[[2007,12,19]],"date-time":"2007-12-19T14:17:11Z","timestamp":1198073831000},"page":"983-988","source":"Crossref","is-referenced-by-count":2,"title":["Analysis and elimination of the output voltage imbalance for a half\u2010bridge boost rectifier under mismatched loads"],"prefix":"10.1002","volume":"36","author":[{"given":"Yu\u2010Kang","family":"Lo","sequence":"first","affiliation":[]},{"given":"Chin\u2010Tse","family":"Ho","sequence":"additional","affiliation":[]},{"given":"Huang\u2010Jen","family":"Chiu","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2007,12,19]]},"reference":[{"key":"e_1_2_1_2_2","doi-asserted-by":"publisher","DOI":"10.1002\/cta.216"},{"key":"e_1_2_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2004.841149"},{"key":"e_1_2_1_4_2","doi-asserted-by":"publisher","DOI":"10.1002\/cta.253"},{"key":"e_1_2_1_5_2","doi-asserted-by":"publisher","DOI":"10.1002\/cta.250"},{"key":"e_1_2_1_6_2","doi-asserted-by":"publisher","DOI":"10.1002\/cta.334"},{"key":"e_1_2_1_7_2","doi-asserted-by":"publisher","DOI":"10.1002\/cta.357"},{"key":"e_1_2_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/63.261023"},{"key":"e_1_2_1_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/63.668112"},{"key":"e_1_2_1_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2002.803243"},{"key":"e_1_2_1_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2005.855676"}],"container-title":["International Journal of Circuit Theory and Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fcta.471","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/cta.471","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,11,14]],"date-time":"2023-11-14T22:52:52Z","timestamp":1700002372000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/cta.471"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,12,19]]},"references-count":10,"journal-issue":{"issue":"8","published-print":{"date-parts":[[2008,11]]}},"alternative-id":["10.1002\/cta.471"],"URL":"https:\/\/doi.org\/10.1002\/cta.471","archive":["Portico"],"relation":{},"ISSN":["0098-9886","1097-007X"],"issn-type":[{"value":"0098-9886","type":"print"},{"value":"1097-007X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2007,12,19]]}}}