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Furthermore, constant bandwidth is achieved by means of switched compensation capacitor arrays. Three\u2010bit prototypes were integrated in a 0.35\u2009\u00b5m\u20133.3\u2009V CMOS process with 2.5\u2009V supply voltage. Experimental distortion levels are better than \u221268\u2009dB for 1\u2009MHz and 1\u2009Vp\u2212p<\/jats:sub>output signals in both configurations; hence, the suitability of the linearization technique based on MOS current dividers is shown. Copyright \u00a9 2007 John Wiley & Sons, Ltd.<\/jats:p>","DOI":"10.1002\/cta.450","type":"journal-article","created":{"date-parts":[[2007,11,15]],"date-time":"2007-11-15T17:20:47Z","timestamp":1195147247000},"page":"397-408","source":"Crossref","is-referenced-by-count":17,"title":["Using MOS current dividers for linearization of programmable gain amplifiers"],"prefix":"10.1002","volume":"36","author":[{"given":"M. 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