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The link is crucial for improving the computational performance of larger systems built from chiplets. To achieve high pin\/energy efficiency and prevent traditional single\u2010ended signaling disadvantages, the transceiver adopts single\u2010ended ground\u2010reference signaling (GRS) to transfer information. To precompensate for the frequency\u2010dependent loss, retain the advantages of GRS, and avoid the disadvantages of traditional AC\u2010coupled equalizer, the transmitter in the transceiver adopts a DC\u2010coupled switched\u2010capacitor charge pump equalizer that can transmit GRS and its equilibrium value can be adjusted according to the channel attenuation. This paper proposes a method for timing de\u2010skew using digital control delay lines to eliminate the timing skew between data and the clock. In addition, this paper presents a duty cycle corrector to avoid duty cycle distortion, with an adjustment range of 44.5% to 52% and a power dissipation of only 30 \nW. The transceiver has an area of 1.016 \n 0.676\u00a0mm2<\/jats:sup>, including one clock lane link and four data lane links. At a nominal 0.8\u2010V power supply voltage, the aggregate eye\u2010opening of the measured 25 Gb\/s data on an organic substrate channel with an attenuation of \u22122.2 dB over 6 mm is 0.675 UI, with a bit error rate (BER) of less than 10\u221212<\/jats:sup> and an energy efficiency of 1.01\u2009pJ\/bit.<\/jats:p>","DOI":"10.1002\/cta.3774","type":"journal-article","created":{"date-parts":[[2023,9,7]],"date-time":"2023-09-07T04:27:42Z","timestamp":1694060862000},"page":"494-512","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A 25\u2010Gb\/s\/pin ground\u2010referenced signaling transceiver with a DC\u2010coupled equalizer for on\u2010package communication"],"prefix":"10.1002","volume":"52","author":[{"ORCID":"http:\/\/orcid.org\/0000-0003-1185-5269","authenticated-orcid":false,"given":"Chao","family":"Guo","sequence":"first","affiliation":[{"name":"Institute of RF and OE\u2010ICs Southeast University Jiangsu China"}]},{"given":"Yingmei","family":"Chen","sequence":"additional","affiliation":[{"name":"Institute of RF and OE\u2010ICs Southeast University Jiangsu China"},{"name":"Pervasive Communication Research Department Purple Mountain Laboratories Jiangsu China"}]},{"given":"Hui","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of RF and OE\u2010ICs Southeast University Jiangsu China"},{"name":"Lab of Modern Detection Technology and Intelligent Systems Huaiyin Normal University Jiangsu China"}]},{"given":"Xu","family":"Chen","sequence":"additional","affiliation":[{"name":"Institute of RF and OE\u2010ICs Southeast University Jiangsu China"}]},{"given":"Chenghao","family":"Wu","sequence":"additional","affiliation":[{"name":"Institute of RF and OE\u2010ICs Southeast University Jiangsu China"}]},{"given":"Yizhou","family":"Zhao","sequence":"additional","affiliation":[{"name":"Institute of RF and OE\u2010ICs Southeast University Jiangsu China"}]}],"member":"311","published-online":{"date-parts":[[2023,9,6]]},"reference":[{"key":"e_1_2_8_2_1","doi-asserted-by":"crossref","unstructured":"MounceG LykeJ HoranS PowellW DoyleR SomeR.Chiplet based approach for heterogeneous processing and packaging architectures. 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