{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,24]],"date-time":"2024-07-24T12:43:27Z","timestamp":1721825007071},"reference-count":27,"publisher":"Wiley","issue":"11","license":[{"start":{"date-parts":[[2021,7,22]],"date-time":"2021-07-22T00:00:00Z","timestamp":1626912000000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Circuit Theory & Apps"],"published-print":{"date-parts":[[2021,11]]},"abstract":"Abstract<\/jats:title>High\u2010speed XOR\u2010XNOR\u2010based hybrid full adder (FA) using a combination of three logic techniques (transmission gate [TG], conventional CMOS [CCMOS], pass transistor [PT]) is presented in this work. Performance analysis and validation of the FA design presented in this work have been realized with reference to 10 state\u2010of\u2010the\u2010art FAs. The scalability of the design has been tested by extending FA up to 32\u2010bits in ripple carry adder (RCA) style. It has been observed that only four existing FAs and the proposed FA could be scaled up to 32\u2010bits without including voltage restoration buffers in the internal stages. The proposed XOR\u2010XNOR\u2010based FA showed excellent performance metrics, both as a 1\u2010bit adder cell as well as in wide word length adder form. Hence, the proposed XOR\u2010XNOR\u2010based hybrid FA can serve as a better alternative to the existing FAs in digital arithmetic blocks of modern microprocessors.<\/jats:p>","DOI":"10.1002\/cta.3109","type":"journal-article","created":{"date-parts":[[2021,7,23]],"date-time":"2021-07-23T05:19:54Z","timestamp":1627017594000},"page":"3597-3606","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":14,"title":["A scalable high\u2010speed hybrid 1\u2010bit full adder design using XOR\u2010XNOR module"],"prefix":"10.1002","volume":"49","author":[{"ORCID":"http:\/\/orcid.org\/0000-0002-5767-6728","authenticated-orcid":false,"given":"Mehedi","family":"Hasan","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering North South University Dhaka Bangladesh"},{"name":"Department of Electrical and Electronic Engineering University of Science and Technology Chittagong Chattogram Bangladesh"}]},{"given":"Sharnali","family":"Islam","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering University of Dhaka Dhaka Bangladesh"}]},{"given":"Mainul","family":"Hossain","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering University of Dhaka Dhaka Bangladesh"}]},{"given":"Hasan U.","family":"Zaman","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering North South University Dhaka Bangladesh"},{"name":"Samsung Austin R&D Center Samsung Corporation Austin Texas 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