{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T02:23:31Z","timestamp":1740104611457,"version":"3.37.3"},"reference-count":21,"publisher":"Wiley","issue":"3","license":[{"start":{"date-parts":[[2017,9,5]],"date-time":"2017-09-05T00:00:00Z","timestamp":1504569600000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Circuit Theory & Apps"],"published-print":{"date-parts":[[2018,3]]},"abstract":"Summary<\/jats:title>Tunnel field\u2010effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we analyze the relationship between devices and register transfer\u2013level architecture choices. We claim that architectural issues should be considered when evaluating this type of transistors because of the differences in delay versus supply voltage behavior exhibited by TFET logic gates with respect to CMOS gates. More specifically, the potential of pipelining and parallelism, both of which rely on lowering supply voltage, as power reduction techniques is evaluated and compared for CMOS and TFET technologies. The results obtained show significantly larger savings in power and energy per clock cycle for the TFET designs than for their CMOS counterparts, especially at low voltages. Pipelining and parallelism make it possibly to fully exploit the distinguishing characteristics of TFETs, and their relevance as competitive TFET circuit design solutions should be explored in greater depth.<\/jats:p>","DOI":"10.1002\/cta.2398","type":"journal-article","created":{"date-parts":[[2017,9,6]],"date-time":"2017-09-06T02:28:45Z","timestamp":1504664925000},"page":"647-655","source":"Crossref","is-referenced-by-count":3,"title":["Impact of the RT\u2010level architecture on the power performance of tunnel transistor circuits"],"prefix":"10.1002","volume":"46","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8345-8441","authenticated-orcid":false,"given":"Mar\u00eda J.","family":"Avedillo","sequence":"first","affiliation":[{"name":"Instituto de Microelectr\u00f3nica de Sevilla, IMSE\u2010CNM (CSIC\/Universidad de Sevilla) Sevilla Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0279-9472","authenticated-orcid":false,"given":"Juan","family":"N\u00fa\u00f1ez","sequence":"additional","affiliation":[{"name":"Instituto de Microelectr\u00f3nica de Sevilla, IMSE\u2010CNM (CSIC\/Universidad de Sevilla) Sevilla Spain"}]}],"member":"311","published-online":{"date-parts":[[2017,9,5]]},"reference":[{"key":"e_1_2_6_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2070470"},{"issue":"4","key":"e_1_2_6_3_1","first-page":"55","article-title":"The tunneling transistor","volume":"2","author":"Seabaugh A","year":"2013","journal-title":"IEEE Spectrum"},{"key":"e_1_2_6_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2014.2326622"},{"key":"e_1_2_6_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2015.2418033"},{"key":"e_1_2_6_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2293135"},{"key":"e_1_2_6_7_1","doi-asserted-by":"publisher","DOI":"10.1038\/nature15387"},{"key":"e_1_2_6_8_1","doi-asserted-by":"publisher","DOI":"10.1038\/nature10679"},{"key":"e_1_2_6_9_1","unstructured":"ChenmingH PatelP BowonderA et al. \u201cProspect of tunneling green transistor for 0.1V CMOS \u201dElectron Devices Meeting IEEE International 16.1.1\/4 2010."},{"key":"e_1_2_6_10_1","doi-asserted-by":"crossref","unstructured":"H.Liu S.Datta V.Narayanan \u201cSteep switching tunnel FET: a promise to extend energy efficient roadmap for post\u2010CMOS digital and analog\/RF applications\u201d Symp. on Low Power and Design.Beijing China;2013.","DOI":"10.1109\/ISLPED.2013.6629285"},{"key":"e_1_2_6_11_1","doi-asserted-by":"crossref","unstructured":"DattaS. BijeshR. LiuH. MohataD.andNarayananV. \u201cTunnel transistors for low power logic\u201d IEEE Compound Semiconductor Integrated Circuit Symposium 1\u20134 2013.","DOI":"10.1109\/CSICS.2013.6659248"},{"issue":"1","key":"e_1_2_6_12_1","first-page":"83","article-title":"Comparison of TFETs and CMOS using optimal design points for power\u2013speed tradeoffs","volume":"16","author":"N\u00fa\u00f1ez J","year":"2017","journal-title":"IEEE Trans Nanotechnol"},{"key":"e_1_2_6_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2616891"},{"key":"e_1_2_6_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2015.2390591"},{"key":"e_1_2_6_15_1","doi-asserted-by":"crossref","unstructured":"SwaminathanK KimMS ChandramoorthyN et al. \u201cModeling steep slope devices: from circuits to architectures\u201d Proceedings Design Automation and Test in Europe Conference.Dresden Germany; March 24\u201028 2014.","DOI":"10.7873\/DATE.2014.149"},{"key":"e_1_2_6_16_1","doi-asserted-by":"crossref","unstructured":"SwaminathanK LiuH LiX et al. \u201cSteep slope devices: enabling new architectural paradigms \u201d2014 51st ACM\/EDAC\/IEEE Design Automation Conference (DAC) San Francisco CA 2014 1\u20136.","DOI":"10.1109\/DAC.2014.6881441"},{"key":"e_1_2_6_17_1","doi-asserted-by":"crossref","unstructured":"SwaminathanK. LiuH. SampsonJ.andNarayananV. \u201cAn examination of the architecture and system\u2010level tradeoffs of employing steep slope devices in 3D CMPs \u201d2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA) Minneapolis MN 2014 241\u2013252.","DOI":"10.1109\/ISCA.2014.6853197"},{"key":"e_1_2_6_18_1","doi-asserted-by":"crossref","unstructured":"AvedilloM. J. N\u00fa\u00f1ezJ. \u201cImpact of pipeline in the power performance of tunnel transistor circuits\u201d.Proceedings of the 26th International Workshop on Power and Timing Modeling Optimization and Simulation (PATMOS).2016.256\u2013261.","DOI":"10.1109\/PATMOS.2016.7833696"},{"key":"e_1_2_6_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2293153"},{"key":"e_1_2_6_20_1","doi-asserted-by":"publisher","DOI":"10.1007\/b101914"},{"key":"e_1_2_6_21_1","unstructured":"LiuH.;SaripalliV.;NarayananV.;S.Datta(2014) \u201cIII\u2010V Tunnel FET Model 1.0.0\u201d https:\/\/nanohub.org\/resources\/21012."},{"key":"e_1_2_6_22_1","unstructured":"ZhaoW.andCaoY. \u201cNew generation of predictive technology model for sub\u201045nm design exploration\u201d Proc. 7th Int. Symp. Quality Electronic Design.San Jose CA USA; March 7\u201029 2006."}],"container-title":["International Journal of Circuit Theory and Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fcta.2398","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/cta.2398","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,26]],"date-time":"2023-09-26T01:42:06Z","timestamp":1695692526000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/cta.2398"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9,5]]},"references-count":21,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2018,3]]}},"alternative-id":["10.1002\/cta.2398"],"URL":"https:\/\/doi.org\/10.1002\/cta.2398","archive":["Portico"],"relation":{},"ISSN":["0098-9886","1097-007X"],"issn-type":[{"type":"print","value":"0098-9886"},{"type":"electronic","value":"1097-007X"}],"subject":[],"published":{"date-parts":[[2017,9,5]]}}}