{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,12]],"date-time":"2023-09-12T07:15:51Z","timestamp":1694502951797},"reference-count":23,"publisher":"Wiley","issue":"6","license":[{"start":{"date-parts":[[2012,6,4]],"date-time":"2012-06-04T00:00:00Z","timestamp":1338768000000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Concurrency and Computation"],"published-print":{"date-parts":[[2013,4,25]]},"abstract":"SUMMARY<\/jats:title>Transactional memory is currently being advocated as a promising alternative to lock\u2010based synchronization because it simplifies multithreaded programming. In this way, future many\u2010core chip multiprocessor architectures may need to provide hardware support for transactional memory. On the other hand, energy consumption constitutes nowadays a first class consideration in multicore processor designs. In this work, we characterize the performance and energy consumption of two well\u2010known hardware transactional memory systems that employ opposite policies for data versioning and conflict management. More specifically, we compare a LogTM\u2010SE eager\u2010eager<\/jats:italic> system and a version of the Scalable Transactional Coherence and Consistency lazy\u2010lazy<\/jats:italic> system that enable parallel commits. To do so, we extended the Multifacet GEMS simulator to estimate the energy consumed in the on\u2010chip caches according to CACTI and used the interconnection network energy model given by Orion 2. Results show that the energy consumption of the eager\u2010eager system is 38% higher in average than in the lazy\u2010lazy case, whereas performance differences between the two systems are 26% in average. We found that even though lazy\u2010lazy beats eager\u2010eager on average, there are considerable deviations in performance depending on the particular characteristics of each application and the settings of both systems. Finally, from this characterization, we observe that a significant part of the energy consumed in some applications in eager\u2010eager is spent on the back\u2010off delay phase and explore more energy\u2010efficient hardware back\u2010off mechanisms. For lazy\u2010lazy systems, the way in which memory lines are assigned to the L2 cache banks affects the number of parallel commits in some applications, and we study an alternative fine\u2010grained assignment. Copyright \u00a9 2012 John Wiley & Sons, Ltd.<\/jats:p>","DOI":"10.1002\/cpe.2866","type":"journal-article","created":{"date-parts":[[2012,6,4]],"date-time":"2012-06-04T19:25:39Z","timestamp":1338837939000},"page":"862-880","source":"Crossref","is-referenced-by-count":4,"title":["On the design of energy\u2010efficient hardware transactional memory\u2009systems"],"prefix":"10.1002","volume":"25","author":[{"given":"E.","family":"Gaona","sequence":"first","affiliation":[{"name":"CAPS Research Group University of Murcia Spain"}]},{"given":"R.","family":"Titos","sequence":"additional","affiliation":[{"name":"CAPS Research Group University of Murcia Spain"}]},{"given":"J.","family":"Fern\u00e1ndez","sequence":"additional","affiliation":[{"name":"CAPS Research Group University of Murcia Spain"}]},{"given":"M. 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