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{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,10,12]],"date-time":"2023-10-12T05:18:14Z","timestamp":1697087894371},"reference-count":25,"publisher":"Wiley","issue":"12","license":[{"start":{"date-parts":[[2010,6,24]],"date-time":"2010-06-24T00:00:00Z","timestamp":1277337600000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Concurrency and Computation"],"published-print":{"date-parts":[[2011,8,25]]},"abstract":"Abstract<\/jats:title>This paper presents the architecture design of a high\u2010efficient and non\u2010memory Advanced Encryption Standard (AES) crypto\u2010core to fit WPAN security requirement. The proposed basis transformation approach from Galois Field (28<\/jats:sup>) to Galois Field GF(((22<\/jats:sup>)2<\/jats:sup>)2<\/jats:sup>) can significantly reduce the hardware complexity of the SubBytes Transformation (S\u2010box). Besides, the on\u2010the\u2010fly key expansion function is used to replace the RAM\u2010based, and the new on\u2010the\u2010fly key scheduler fully supports AES\u2010128, AES\u2010192 and AES\u2010256. Moreover, resource\u2010sharing scheme will also be employed to reduce the hardware complexity of the cipher and decipher. FPGA experiment results show that the AES core works at 175.75\u2009MHz clock. It takes about 33 clocks and 66 clocks to complete an AES\u2010128 encryption and decryption, respectively. That is, the corresponding throughputs are 681.7 and 340.85\u2009Mbps. The hardware cost of the AES design is about 2420 slices with 3\u2010in\u20101 key scheduler included. Experiment results also show that the proposed design is suitable for integration into the WPAN chips due to its acceptable power dissipation. Copyright \u00a9 2010 John Wiley & Sons, Ltd.<\/jats:p>","DOI":"10.1002\/cpe.1619","type":"journal-article","created":{"date-parts":[[2010,6,25]],"date-time":"2010-06-25T01:22:05Z","timestamp":1277428925000},"page":"1332-1347","source":"Crossref","is-referenced-by-count":3,"title":["Architecture design of high\u2010efficient and non\u2010memory AES crypto\u2010core for WPAN"],"prefix":"10.1002","volume":"23","author":[{"given":"Rong\u2010Jian","family":"Chen","sequence":"first","affiliation":[]},{"given":"Jun\u2010Jian","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Su\u2010Min","family":"Hung","sequence":"additional","affiliation":[]},{"given":"Jui\u2010Lin","family":"Lai","sequence":"additional","affiliation":[]},{"given":"Shi\u2010Jinn","family":"Horng","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2011,8,7]]},"reference":[{"key":"e_1_2_8_2_2","unstructured":"IEEE 802.15 WPAN Task Group 1 (TG1). Available at:http:\/\/www.ieee802.org\/15\/pub\/TG1.html[April2010]."},{"key":"e_1_2_8_3_2","unstructured":"IEEE 802.15 WPAN\u2122Task Group 4 (TG4). Available at:http:\/\/www.ieee802.org\/15\/pub\/TG4.html[April2010]."},{"key":"e_1_2_8_4_2","unstructured":"IEEE 802.15 WPAN Task Group 3 (TG3). Available at:http:\/\/www.ieee802.org\/15\/pub\/TG3.html[April2010]."},{"key":"e_1_2_8_5_2","unstructured":"IEEE 802.15 WPAN High Rate Alternative PHY Task Group 3a (TG3a). Available at:http:\/\/www.ieee802.org\/5\/pub\/TG3a.html[April2010]."},{"key":"e_1_2_8_6_2","volume-title":"Data Encryption Standard (DES)","author":"National Institute of Standards and Technology (NIST)","year":"1999"},{"key":"e_1_2_8_7_2","doi-asserted-by":"publisher","DOI":"10.6028\/NIST.FIPS.197"},{"key":"e_1_2_8_8_2","volume-title":"Cryptography and Network Security: Principles and Practice","author":"Stallings W","year":"2003"},{"key":"e_1_2_8_9_2","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0052343"},{"key":"e_1_2_8_10_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-39887-5_17"},{"key":"e_1_2_8_11_2","series-title":"Lecture Notes in Computer Science","first-page":"103","volume-title":"Proceedings of the Selected Areasin Cryptography (SAC) 2003","author":"Ferguson N","year":"2003"},{"key":"e_1_2_8_12_2","unstructured":"DaemenJ RijmenV. AES Proposal: Rijndael AES algorithm submission. Available at:http:\/\/www.nist.gov\/CryptoToolkit[September2009]."},{"key":"e_1_2_8_13_2","unstructured":"Draft FIPS for the AES. Available at:http:\/\/csrc.nist.gov\/encryption.aes[February2001]."},{"key":"e_1_2_8_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.832943"},{"key":"e_1_2_8_15_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2004.12.001"},{"key":"e_1_2_8_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.49"},{"key":"e_1_2_8_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2003.1252803"},{"key":"e_1_2_8_18_2","doi-asserted-by":"crossref","unstructured":"McLooneM McCannyJ.High performance single\u2010chip FPGA Rijndael algorithm implementations. Proceedings of Cryptographic Hardware and Embedded Systems Workshop CHES Paris May 2001.","DOI":"10.1007\/3-540-44709-1_7"},{"key":"e_1_2_8_19_2","doi-asserted-by":"crossref","unstructured":"JarvinenKU TommiskaMT SkyttaJO.A fullypipelined memoryless 17.8\u2009Gbps AES\u2010128 encryptor. Proceedings of International Symposium on Field\u2010programmable Gate Arrays (FPGA 2003) Monterey CA February 2003;207\u2013215.","DOI":"10.1145\/611817.611848"},{"key":"e_1_2_8_20_2","doi-asserted-by":"crossref","unstructured":"SaggeseGP MazzeoA MazoccaN StrolloAGM.An FPGA\u2010based performance analysis of the unrolling tiling and pipelining of the AES algorithm. Proceedings of FPL 2003 Portugal September 2003.","DOI":"10.1007\/978-3-540-45234-8_29"},{"key":"e_1_2_8_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/92.931230"},{"key":"e_1_2_8_22_2","doi-asserted-by":"crossref","unstructured":"StandaertF RouvroyG QuisquaterJ LegatJ.Efficient implementation of Rijndael encryption in reconfigurable hardware: improvements & design tradeoffs. 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